- 25 Feb, 2010 3 commits
-
-
Ben Skeggs authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
-
Ben Skeggs authored
PFIFO on G80 and up has a new mode where the main ring buffer is simply a ring of pointers to indirect buffers containing the actual command/data packets. In order to be able to implement index buffers in the 3D driver we need to be able to submit data-only push buffers right after the cmd packet header, which is only possible using the new command submission method. This commit doesn't make it possible to implement index buffers yet, some userspace interface changes will be required, but it does allow for testing/debugging of the hardware-side support in the meantime. Signed-off-by: -
Maarten Maathuis authored
The nv50 pgraph handler (for example) could reenable pgraph fifo access and that would be bad when pgraph context is being unloaded (we need the guarantee a ctxprog isn't running). Signed-off-by:
Maarten Maathuis <madman2003@gmail.com> Signed-off-by:
-
- 23 Feb, 2010 6 commits
-
-
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
This also modifies the unused PRAMIN PT entries to be all zeroes, can't really recall why I used 9/0 initially, just that it didn't work for some reason. It was likely masking a bug elsewhere that's since been fixed. Signed-off-by: -
Ben Skeggs authored
This commit changes nouveau to construct PTEs which look very much like the ones the binary driver creates. I presume that filling multiple PTEs identically with length flags and the physical address of the start of a block of VRAM is a hint to the memory controller that it need not perform additional page table lookups for that range of addresses. Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
GART is handled elsewhere, no reason to have the code for it here too. Signed-off-by: -
Francisco Jerez authored
Signed-off-by:
Francisco Jerez <currojerez@riseup.net> Signed-off-by:
-
- 16 Feb, 2010 2 commits
-
-
Francisco Jerez authored
Signed-off-by:
-
Ben Skeggs authored
Signed-off-by:
-
- 10 Feb, 2010 2 commits
-
-
Matthew Garrett authored
Signed-off-by:
Matthew Garrett <mjg@redhat.com> Signed-off-by:
-
Marcin Slusarz authored
Reported-by:
Dan Carpenter <error27@gmail.com> Signed-off-by:
Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by:
-
- 09 Feb, 2010 16 commits
-
-
Maarten Maathuis authored
Unset the bit that indicates that a ctxprog can continue at the end. Signed-off-by:
-
Maarten Maathuis authored
ramfc is zero'ed upon destruction, so it's safer to do things in the right order. Signed-off-by:
-
Maarten Maathuis authored
- We need to disable pgraph fifo access before checking the current channel, otherwise we could still hit a running ctxprog. - The writes to 0x400500 are already handled by pgraph->fifo_access and are therefore redundant, moreover pgraph fifo access should not be reenabled before current context is set as invalid. So remove them altogether. Signed-off-by:
-
Maarten Maathuis authored
- In the current situation the padding that is added is dangerous to write to, userspace could potentially overwrite parts of another bo. - Depth and stencil buffers are supposed to be large enough in general so the waste of memory should be acceptable. - Alternatives are hiding the padding from users or splitting vram into 2 zones. Signed-off-by:
-
Ben Skeggs authored
Fixes DVI+VGA on my 9400, and likely a lot of other configurations that got broken by the previos DVI-over-DP fix. Signed-off-by: -
Ben Skeggs authored
With DVI and DP plugged, the DVI clock change interrupts being run can cause DP link training to fail. This adds a spinlock around init table parsing to prevent this. Signed-off-by: -
Ben Skeggs authored
Writes don't return a count, and adding the check broke native DP. Signed-off-by: -
Ben Skeggs authored
It appears we aren't required to do memory sizing ourselves on nv40 either. NV40 init tables read a strap from PEXTDEV_BOOT_0 into a CRTC register, and then later use that value to select a memory configuration (written to PFB_CFG0, just like INIT_COMPUTE_MEM on earlier cards) with INIT_IO_RESTRICT_PROG. Signed-off-by: -
Marcin Kościelnicki authored
Signed-off-by:
Marcin Kościelnicki <koriakin@0x04.net> Signed-off-by:
-
Marcin Kościelnicki authored
We used single shared fbops struct and patched it at fb init time with pointers to the right variant. On mixed multicard, this meant that it was either sending NV50-style commands to all cards, or NV04-style commands to all cards. Signed-off-by:
-
Julia Lawall authored
Test the just-allocated value for NULL rather than some other value. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression x,y; statement S; @@ x = \(kmalloc\|kcalloc\|kzalloc\)(...); ( if ((x) == NULL) S | if ( - y + x == NULL) S ) // </smpl> Signed-off-by:
Julia Lawall <julia@diku.dk> Cc: David Airlie <airlied@linux.ie> Cc: Ben Skeggs <bskeggs@redhat.com> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
-
Luca Barbieri authored
nouveau_gem_ioctl_cpu_prep calls ttm_bo_wait without the bo lock held. ttm_bo_wait unlocks that lock, and so must be called with it held. Currently this bug causes libdrm nouveau_bo_busy() to hang the machine. Signed-off-by: Luca Barbieri <luca at luca-barbieri.com> Acked-by:
-
Francisco Jerez authored
Apparently, they generate a PFIFO interrupt each time one of the semaphore methods is executed if its ctxdma wasn't manually marked as valid. This patch makes it flip the valid bit in response to the DMA_SEMAPHORE method (which triggers the IRQ even for a valid ctxdma). Signed-off-by:
-
Marcin Kościelnicki authored
On nv50, this will be needed by applications using CUDA to know how much stack/local memory to allocate. Signed-off-by:
-
Marcin Kościelnicki authored
noaccel=1 disables all acceleration and doesn't even attempt initialising PGRAPH+PFIFO, nofbaccel=1 only makes fbcon unaccelerated. Signed-off-by:
-
Ben Skeggs authored
Due to a thinko, these were previously forced to VRAM even if we allocated them in GART. This commit fixes that bug, but keeps the previous behaviour of using VRAM by default until it's been tested properly across more chipsets. Signed-off-by:
-
- 25 Jan, 2010 4 commits
-
-
Ben Skeggs authored
Another hack because of us exposing each encoder block's function as an encoder rather than exposing a single encoder that deals with them all. A proper fix will come, it's just rather invasive so this hack will do until then. Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
We need to add the buffer to the list even if we fail, otherwise the validate_fini() call won't unreserve + unreference the GEM object, making TTM very unhappy. Signed-off-by: -
Ben Skeggs authored
Also adds a module option to ignore the status reported via ACPI, in case we hit systems with broken ACPI. Signed-off-by:
-
- 17 Jan, 2010 6 commits
-
-
Ben Skeggs authored
On most cards the DisplayPort connector is created with 2 encoders sharing a single SOR (for native DP, and for DVI-over-DP). The previous logic for turning off unused encoders didn't take into account that we could have multiple drm_encoders on a single hw encoder and ended up turning off encoders that were actually being used still. This patch fixes that issue. We probably want to look at something a bit better later on, and only expose one drm_encoder per hw encoder block. Signed-off-by: -
Ben Skeggs authored
GPU pointer to the structure is shifted right by 10 bits, so we need to align to 1024 bytes, not 256. Reported-by:
-
Luca Barbieri authored
Currently, we take down the sgdma engine without evicting all buffers from VRAM. The TTM device release will try to evict anything in VRAM to GART memory, but this will fail since sgdma has already been taken down. This causes an infinite loop in kernel mode on module unload. It usually doesn't happen because there aren't any buffer on close. However, if the GPU is locked up, this condition is easily triggered. This patch fixes it in the simplest way possible by cleaning VRAM right before cleaning SGDMA memory. Signed-off-by:
Luca Barbieri <luca@luca-barbieri.com> Signed-off-by:
-
Luca Barbieri authored
Currently Nouveau is unable to dismiss DMA_VTX_PROTECTION errors, which results in an infinite loop in the interrupt handler. These errors are caused both by bugs in the Gallium driver and by user-specified index buffers with out of bounds indices. By mmio-tracing the nVidia drivers, I found out how this is done. On DMA_VTX_PROTECTION, The nVidia driver reads the register 0x402000, always getting the value 4, and then writes 4 back to 0x402000. This patch adds that logic by reading 0x402000 and writing the same value back. It's unclear what should happen if the value read is not 4, and the current approach might not be the correct one. To test this, modify mesa/progs/trivial/vbo-drawrange.c, defining ELTOBJ to 1 and replacing indices with huge out of bounds integers. Without this patch, the GPU and/or kernel should lock up. With this patch, it should misrender as expected but not lock up. The errors are still logged since they are useful for development. This has been tested on NV49 and may not work on other cards. To find out how things work on other cards, run the aforementioned test using the blob with mmiotrace and grep for a read of the PGRAPH source register. Signed-off-by:
-
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Can be triggered easily on certain cards (NV46 and NV50 of mine) by running "dmesg", the DRM's channel will lockup. Signed-off-by:
-
- 14 Jan, 2010 1 commit
-
-
Luca Barbieri authored
Currently there is no check that the pushbuffer request bounds are inside the TTM BO. This allows to instruct the kernel to do relocations on user-selected addresses, since the relocation bounds checking relies on the request bounds. This can oops the kernel accidentally and is easily exploitable. This patch adds bound checking and alignment checking for ->offset and ->nr_dwords. It also makes some variables unsigned, which should have no effect, but prevents possible bounds checking problems. Signed-off-by:
-
