- 15 Mar, 2018 17 commits
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Rex Zhu authored
make it symmetric with amdgpu_ucode_init_bo in amd_powerplay.c refine the "commit b22558bb4ff8fc9fe925222f90297d7a03a5fb20" Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
1. delete amdgpu_powerplay.c used for wrapping smu ip functions 2. delete struct pp_instance, 3. make struct hwmgr as the smu hw handle. Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
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Christian König <christian.koenig@amd.com> Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
Powerplay is for the hw ip smu, for RV, smu10 is used, so use smu10 as the prefix of the files name/function name. Reviewed-by:
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Rex Zhu authored
caused by "commit dcefb7668e5b4fb56099b16d1790cd3056322b03" Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
In send_message_to_smu helper functions, Print out the error code for debug if smu failed to response. The helper functions always return true, so no need to check their return value. Reviewed-by:
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Rex Zhu authored
1. There is a race condition when another ip also use same register pairs 2. check once at boot up by GetDriverIfVersion message is sufficient to check SMU health. so delete is_smc_ram_running check. Reviewed-by:
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Rex Zhu authored
smu7_smumgr.h should not be included in rv and vega, The common functions for all smu7 asics are put in smu_smumgr.c. Not include cgs interface in smumgr.c. the code used cgs interface has been deleted. Not include smu_ucode_xfer_vi.h in rv/vega Reviewed-by:
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Rex Zhu authored
Free the backend structure if we fail to allocate device memory. Reviewed-by:
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Rex Zhu authored
AVFS feature support/not support is enough to driver. so remove the complex define of the avfs btc state. Reviewed-by:
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Andrey Grodzovsky authored
Reusing local handle to initialize BO without resetting it to NULL is wrong since it causes amdgpu_bo_create_reserved to skip new BO creation and just reuse the given pointer for pinning. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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- 14 Mar, 2018 23 commits
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Feifei Xu authored
Remove mmhub header files inclusion which not used. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
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Alex Deucher authored
Rather then relying on the asic type for the second instance. Makes it more consistent with the rest of the code. Reviewed-by:
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Alex Deucher authored
no intended functional change. Reviewed-by:
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Alex Deucher authored
Free the backend structure if we fail to allocate device memory. Reviewed-by:
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Michel Dänzer authored
Turning off the sink in this case causes various issues, because userspace expects it to stay on until it turns it off explicitly. Instead, turn the sink off and back on when a display is connected again. This dance seems necessary for link training to work correctly. Bugzilla: https://bugs.freedesktop.org/105308 Cc: stable@vger.kernel.org Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Colin Ian King authored
The pointer internal_buf is assigned a value but the pointer is never read, hence it is redundant and can be removed. Cleans up clang warning: drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/smu7_smumgr.c:630:2: warning: Value stored to 'internal_buf' is never read Reviewed-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
No need to replicate it in several places. Reviewed-by:
Rex Zhu <rezhu@amd.com> Acked-by:
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Alex Deucher authored
Regardless of whether the user has selected psp fw loading or not. It's still needed for GPU reset among other things. There are already guards in place to avoid setting up the full psp if PSP fw loading is not enabled. Reviewed-by:
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Alex Deucher authored
The per device firmware load method is limited to what makes sense for that asic rather than whatever arbitrary value may have been set by the user. Reviewed-by:
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Alex Deucher authored
No need to replicate it in several places. Reviewed-by:
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Alex Deucher authored
We already checked and returned early in most of the IP functions, fill in the rest as well. Reviewed-by:
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Shirish S authored
This patch adds an essential check related to the size of the payload to be transferred via aux channel. Without this check dal_ddc_service_read_dpcd_data() is fed with inappropriate payload size leading to deadlocks. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
We have unused variables being populated when notifying pplib. This change amends that. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Yongqiang Sun authored
root cause: DMCU try to perform a smoothness brightness change.Incorrect initial brightness level causes the 1 sec dim. Change: Cache brightness level in stream, and clear it when edp backlight on. If brightness level in stream is 0, set brightness with ramp value is 0. DMCU will set the brightness without smoothness transition. v2: squash in null pointer fix (Harry) Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Jerry (Fangzhi) Zuo authored
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Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Harry Wentland authored
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Oak Zeng authored
This is preparation for sharing client ID definitions between amdgpu and amdkfd Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Bw spreadsheet was updated while dce_calcs was not Signed-off-by:
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Yongqiang Sun authored
Increase clock, if current dpp div is 0 and request dpp div is 1, request clk is higher than maximum dpp clk as per dpm table. set dispclk to the value of maximum supported dpp clk set div to 1 set dispclk to request value. Decrease clock, currrent dpp div is 1 and request dpp div is 0, current clk is higher than maximum dpp clk as per dpm table. set dispclk to the value of maximum supported dpp clk set div to 0 set dispclk to request value. v2: squash in !DCN build fix Signed-off-by:
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Samson Tam authored
Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Shirish S authored
The order of planes is given by the order they are enumerated by kms. Planes with a higher ID appears above planes with a lower ID. Currently the planes are enumerated in the wrong order, putting the nv12 only plane after the two RGBA planes. This patch corrects the plane enumeration order such that all the overlay planes are initialized first then the primary planes. Due to this change in order the dc_add_plane_to_context() shall receive the planes in reverse order hence this patch reverses the parsing of planes in DM side itself. v2: drop local reverse macro for upstream Signed-off-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by:
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Vitaly Prosyak authored
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Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Tony Cheng authored
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