- 13 Sep, 2017 9 commits
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Chris Wilson authored
As realised by commit 9e3d6223 ("math64, timers: Fix 32bit mul_u64_u32_shr() and friends"), GCC does not always generate ideal code for performing a 32b x 32b multiply returning a 64b result (i.e. where we idiomatically use u64 result = (u64)x * (u32)x). This catches a couple of instances in the display code using (u64)x * (u32)y. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20170913105154.2910-1-chris@chris-wilson.co.ukReviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com>
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Chris Wilson authored
The sgt iterators cause an drivers/gpu/drm/i915/i915_gpu_error.c:846 i915_error_object_create() warn: statement has no effect 7 everywhere they are used. If we change the code slightly, we can achieve the same increment without altering the output or raising a warning. text data bss dec hex filename 1267906 20587 3168 1291661 13b58d before 1267906 20587 3168 1291661 13b58d after Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170913105754.4423-1-chris@chris-wilson.co.uk
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Oscar Mateo authored
Spare some comments and other small style changes. Suggested-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by:
Oscar Mateo <oscar.mateo@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1505252197-27696-3-git-send-email-oscar.mateo@intel.comReviewed-by:
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Oscar Mateo authored
We never used it in i915 and it's going to be removed in newer GuC firmwares anyway. Signed-off-by:
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Oscar Mateo authored
The default values for the default scheduling policy come from the GuC firmware itself. Transform the magic numbers into defines. Suggested-by:
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Chris Wilson authored
The context descriptor is stored inside the per-engine context state, as we only need to compute it once and access it frequently. However, currently only intel_lrc.c has easy access, but i915_guc_submission.c would like to frequently read it as well, and more so only ever needs the lower 32bits. Make it an inline as the compiler should be able to retrieve the value in less instructions than it takes to do the function call: add/remove: 0/1 grow/shrink: 1/0 up/down: 8/-45 (-37) function old new delta i915_guc_submit 621 629 +8 intel_lr_context_descriptor 45 - -45 Signed-off-by:
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Mika Kahola authored
Error message indicating that the same MIPI command is sent consecutively is perhaps too strongly said. Let's replace that as a debug message instead. Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Lee, Shawn C authored
Min brightness value from vbt was missing for CNP platform. This setting have to refer backlight ic spec to restrict min backlight output. Without this restriction, driver would allow to configure lower brightness value and violate backlight ic requirement. Fixes: 4c9f7086 ("drm/i915/cnp: Backlight support for CNP.") Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Shawn Lee <shawn.c.lee@intel.com> Signed-off-by:
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Uma Shankar authored
This reverts commit bbdf0b2f ("drm/i915/bxt: Disable device ready before shutdown command"). Disable device ready before shutdown command was added previously to avoid a split screen issue seen on dual link DSI panels. As of now, dual link is not supported and will need some rework in the upstream code. For single link DSI panels, the change is not required. This will cause failure in sending SHUTDOWN packet during disable. Hence reverting the change. Will handle the change as part of dual link enabling in upstream. Fixes: bbdf0b2f ("drm/i915/bxt: Disable device ready before shutdown command") Cc: <stable@vger.kernel.org> # v4.12+ Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by:
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- 12 Sep, 2017 7 commits
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Chris Wilson authored
Following the simplification to a single lookup loop in commit 170fa29b ("drm/i915: Simplify eb_lookup_vmas()") and commit d1b48c1e ("drm/i915: Replace execbuf vma ht with an idr"), we can go one step further and reorder the error paths so that the state of the local variable obj is always known to the compiler and doesn't need the uninitialized_var markup to squelch a compiler warning. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Dhinakaran Pandiyan authored
The SDE interrupt bits 25, 26 and 27 are either reserved or meant for DDI E hotplug in SPT+. These bits are meant for AUX channels only in LPT and CPT, so add the appropriate checks. Signed-off-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ville Syrjälä authored
Give a name to the bit which tells pcode to control IPS. v2: Note that IPS_CTL bits apply to DISPLAY_IPS_CONTROL as well (Chris) Signed-off-by:
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Ville Syrjälä authored
Signed-off-by:
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Zhi Wang authored
Factor out setup_private_pat() for introducing the following patches. Signed-off-by:
Zhi Wang <zhi.a.wang@intel.com> Cc: Ben Widawsky <benjamin.widawsky@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by:
Ben Widawsky <benjamin.widawsky@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1505202148-22959-1-git-send-email-zhi.a.wang@intel.comSigned-off-by:
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Lee, Shawn C authored
Min brightness value from vbt was missing for BXT platform. This setting have to refer backlight ic spec to restrict min backlight output. Without this restriction, driver would allow to configure lower brightness value and violate backlight ic requirement. Fixes: 0fb890c0 ("drm/i915/bxt: BLC implementation") Cc: Jani Nikula <jani.nikula@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: Gary C Wang <gary.c.wang@intel.com> Signed-off-by:
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Marta Lofstedt authored
During IGT testing it has been shown that the specification defined polling time of 1 us for FCLK_DONE, is sometimes not enough. The issue is still reproducible while disabling C-states through the PM QoS framework and also while disabling preemtion. From this the most plausible explanation is that the issue is due to a firmware flaw. As a workaround, it is better to wait a little bit longer for the FCLK_DONE to come around, than to leave with an DRM_ERROR and having FCLK_DONE at a randome time after. While spinning a list of igt tests prone to reproduce the issue the FCLK_DONE poll failed at approximately 2% of the invocations of the bdw_set_cdclk function. The longest poll time during this testing was measured to ~7us. So, the suggested new poll time of 100us is on the safe side. v2: Added more documentation about investigations done. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102243Signed-off-by:
Marta Lofstedt <marta.lofstedt@intel.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170908132829.6312-1-marta.lofstedt@intel.com
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- 11 Sep, 2017 12 commits
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Rodrigo Vivi authored
Continue on VLV PSR split with vfunc, let's also create one for enabling source. Also since we are touching *_enable_source functions let's fix a comment with wrong name for vlv's one. v2: Fix typo on commit message (DK). Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by:
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Rodrigo Vivi authored
Continue on VLV PSR split with vfunc, let's also create one for enabling sink. v2: Fix typo on commit message (DK). Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by:
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Rodrigo Vivi authored
Continue on VLV PSR split with vfunc, let's also create one for setting up VSC. v2: Rebased on top of commit d2419ffc ("drm/i915: Plumb crtc_state to PSR enable/disable") Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by:
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Rodrigo Vivi authored
Let's move the activation calls together after enable is done. No real functional change should be expected here. Just an attempt to get it clear when we are really activating PSR after enabling it. v2: Add braces on if/else because commit message there is too long as suggested by Jani. v3: Rebased on top of commit d2419ffc ("drm/i915: Plumb crtc_state to PSR enable/disable") Cc: Jani Nikula <jani.nikula@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by: -
Rodrigo Vivi authored
No functional change is expected here since at this point PSR is not allowed to go to any active state. In other words, not really enabled. However let's do in a separated patch so it gets clear on what is change and specially it can helps on bisect case if we figure something has caused changes in behaviour. But this needs to be done before we make the vfunc to enable source to be in parity with VLV implementation. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by:
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Rodrigo Vivi authored
This sequence is part of enable source anyways, but they only need to be executed once and not on every activation, So let's re-create hsw_enable_source. v2: Avoid changing order here to avoid changing behaviour as suggested by Jani. v3: Rebased on top of commit d2419ffc ("drm/i915: Plumb crtc_state to PSR enable/disable") Cc: Jani Nikula <jani.nikula@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by: -
Rodrigo Vivi authored
VSC package is decided per eDP spec for psr1 or psr2, and not per platform, so let's unify it and kill "skl" func. v2: Rebased on top of commit d2419ffc ("drm/i915: Plumb crtc_state to PSR enable/disable") Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by:
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Rodrigo Vivi authored
Continue on VLV PSR split with vfunc, let's move activate function there. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by:
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Rodrigo Vivi authored
On HSW+ the real activate of PSR is decided by the source after certain amount of configured idle frames. However for the driver perspective where we track psr.active variable this function here is the actual activate one. So let's rename it before moving to vfunc with that. v2: Fix typo on commit message (DK). Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by:
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Rodrigo Vivi authored
VLV/CHV has a total different PSR implementation than the other platforms, so let's start moving that to vfuncs. Let's start with disable_src one. v2: Rebased on top of commit d2419ffc ("drm/i915: Plumb crtc_state to PSR enable/disable") Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by:
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Rodrigo Vivi authored
We really don't want to setup vfuncs and lock mutexes on platforms that has no support to PSR. Also we know what platforms they are so let's do it quietly. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by:
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Christophe JAILLET authored
We should go through the error handling path to decrease the 'framebuffer_references' as done everywhere else in this function. Fixes: 2e2adb05 ("drm/i915: Add render decompression support") Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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- 09 Sep, 2017 1 commit
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Chris Wilson authored
If we know that we will completely fill a pagetable (i.e. we are inserting a complete set of 512 pages), we can skip prefilling that PT with scratch entries. If we have to abort the insertion prior to writing the real entries, we will teardown the pagetable and remove it from the page directory (so that we will restart the allocation next time). We could do similar tricks for the PD and PDP, but the likelihood of a single insertion covering the entire 512 entries diminishes, as do the cycle savings. The saving are even greater (relatively) when we are preallocating page tables for huge pages, as then we never need to fill the page table. Signed-off-by:
Matthew Auld <matthew.auld@intel.com>
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- 08 Sep, 2017 11 commits
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Michal Wajdeczko authored
Macro params shall be wrapped into () to avoid unexpected results. Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170908161130.22424-1-michal.wajdeczko@intel.comReviewed-by:
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Michel Thierry authored
Gen7 won't get any new engines, and we already added VCS2 there to just silence gcc's not handled in switch warnings. Use a default case instead, otherwise we will need to keep adding extra cases if changes happen in the future. v2: Since reaching the default case is impossible, use GEM_BUG_ON (Chris). Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170830180115.907-1-michel.thierry@intel.comReviewed-by:
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https://github.com/01org/gvt-linuxJani Nikula authored
gvt-next-2017-09-08 - PCI config sanitize series (Changbin) - Workload submission error handling series (Fred) Signed-off-by:
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Changbin Du authored
IGD is PCIe device and has extended configuration space. Checking the binary dump, we can see we have Caps located out of PCI compatible Configuration Space range. 0x000: 86 80 12 19 17 04 10 00 06 00 00 03 00 00 00 00 0x010: 04 00 00 10 08 00 00 00 0c 00 00 00 08 00 00 00 0x020: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b9 06 0x030: 00 f8 ff ff 40 00 00 00 00 00 00 00 0b 01 00 00 0x040: 09 70 0c 01 71 26 01 62 c8 00 04 84 00 00 00 00 0x050: c1 00 00 00 39 00 00 00 00 00 00 00 01 00 00 a2 0x060: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 0x070: 10 ac 92 00 00 80 00 10 00 00 00 00 00 00 00 00 0x080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x0a0: 00 00 00 00 00 00 00 00 00 00 00 00 05 d0 01 00 0x0b0: 18 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00 0x0c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x0d0: 01 00 22 00 00 80 00 00 00 00 00 00 00 00 00 00 0x0e0: 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 0x0f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x100: 1b 00 01 20 02 14 00 00 00 00 00 00 00 00 00 00 ... Currently, we only emulate the PCI compatible Configuration Space. This is okay if we attach vGPU to PCI bus. But when we attach to a PCI Express bus (when Qemu emulates a Intel Q35 chipset which has PCIe slot), it will not work. Extended Configuration Space is required for a PCIe device. This patch extended the virtual configuration space from 256 bytes to 4KB bytes. So we are to be a *real* PCIe device. And for the Extended CapList we keep same to physical GPU. Cc: Laszlo Ersek <lersek@redhat.com> Tested-by:
Laszlo Ersek <lersek@redhat.com> Signed-off-by:
Changbin Du <changbin.du@intel.com> Signed-off-by:
Zhenyu Wang <zhenyuw@linux.intel.com>
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Changbin Du authored
Looking at our virtual PCI device, we can see surprising Region 4 and Region 5. 00:10.0 VGA compatible controller: Intel Corporation Sky Lake Integrated Graphics (rev 06) (prog-if 00 [VGA controller]) .... Region 0: Memory at 140000000 (64-bit, non-prefetchable) [size=16M] Region 2: Memory at 180000000 (64-bit, prefetchable) [size=1G] Region 4: Memory at <ignored> (32-bit, non-prefetchable) Region 5: Memory at <ignored> (32-bit, non-prefetchable) Expansion ROM at febd6000 [disabled] [size=2K] The fact is that we only implemented BAR0 and BAR2. Surprising Region 4 and Region 5 are shown because we report their size as 0xffffffff. They should report size 0 instead. BTW, the physical GPU has a PIO BAR. GVTg hasn't implemented PIO access, so we ignored this BAR for vGPU device. v2: fix BAR size value calculation. Link: https://bugzilla.redhat.com/show_bug.cgi?id=1458032Signed-off-by: -
fred gao authored
fix the wrong return type and return error once the unknown command is scanned. v2: - separate this error handle from healthy rating code. (Zhenyu) Signed-off-by:
fred gao <fred.gao@intel.com> Signed-off-by:
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fred gao authored
When an error occurs in dispatch_workload, this patch is to do the proper cleanup and rollback to the original states before the workload is abandoned. v2: - split the mixed several error paths for better review. (Zhenyu) v3: - original PTR_ERR(cs) is good and code cleanup. (Zhenyu) v4: - reuse the existing i915_add_request for error handling. (Zhenyu) v5: - remove the duplicate error handling release_shadow_wa_ctx and move the engine->context_unpin upper. (Zhenyu) v6: - keep the old label "out". (Zhenyu) Signed-off-by:
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fred gao authored
When it is failed in shadow_mm, the pin_count should rollback to the original states before return. v2: - split the mixed several error paths for better review. (Zhenyu) v3: increase the pincount after shadow success. (Zhenyu) Signed-off-by:
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fred gao authored
refine the error handling for prepare_execlist_workload to restore to the original states once error occurs. only release the shadowed batch buffer and wa ctx when the workload is completed successfully. v2: - split the mixed several error paths for better review. (Zhenyu) v3: - handle prepare batch buffer/wa ctx pin errors and - emulate_schedule_in null issue. (Zhenyu) v4: - no need to handle emulate_schedule_in null issue. (Zhenyu) v5: - release the shadowed batch buffer and wa ctx only for the successful workload. (Zhenyu) v6: - polish the return style. (Zhenyu) Signed-off-by:
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fred gao authored
When an error occurs after shadow_indirect_ctx, this patch is to do the proper cleanup and rollback to the original states for shadowed indirect context before the workload is abandoned. v2: - split the mixed several error paths for better review. (Zhenyu) v3: - no return check for clean up functions. (Changbin) v4: - expose and reuse the existing release_shadow_wa_ctx. (Zhenyu) v5: - move the release function to scheduler.c file. (Zhenyu) v6: - move error handling code of intel_gvt_scan_and_shadow_workload to here. (Zhenyu) Signed-off-by:
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fred gao authored
Currently i915 request structure and shadow ring buffer are allocated before command scan, so it will have to restore to previous states once any error happens afterwards in the long dispatch_workload path. This patch is to introduce a reserved ring buffer created at the beginning of vGPU initialization. Workload will be coped to this reserved buffer and be scanned first, the i915 request and shadow ring buffer are only allocated after the result of scan is successful. To balance the memory usage and buffer alloc time, the coming bigger ring buffer will be reallocated and kept until more bigger buffer is coming. v2: - use kmalloc for the smaller ring buffer, realloc if required. (Zhenyu) v3: - remove the dynamically allocated ring buffer. (Zhenyu) v4: - code style polish. - kfree previous allocated buffer once kmalloc failed. (Zhenyu) Signed-off-by:
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