- 12 Oct, 2007 40 commits
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Jeff Garzik authored
* Introduce pci_domains_supported global, hardcoded to zero if !CONFIG_PCI_DOMAINS. * Introduce 'nodomains' boot option, which clears pci_domains_supported on platforms that enable it by default (x86, x86-64, and others when they are converted to use this). Signed-off-by:
Jeff Garzik <jgarzik@redhat.com> Cc: Andi Kleen <ak@suse.de> Signed-off-by:
Greg Kroah-Hartman <gregkh@suse.de>
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Gary Hade authored
Modify PCI Bridge Control ISA flag for clarity This patch changes PCI_BRIDGE_CTL_NO_ISA to PCI_BRIDGE_CTL_ISA and modifies it's clarifying comment and locations where used. The change reduces the chance of future confusion since it makes the set/unset meaning of the bit the same in both the bridge control register and bridge_ctl field of the pci_bus struct. Signed-off-by:
Gary Hade <garyhade@us.ibm.com> Acked-by:
Linas Vepstas <linas@austin.ibm.com> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Signed-off-by:
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Gary Hade authored
Use _CRS for PCI resource allocation This patch resolves an issue where incorrect PCI memory and i/o ranges are being assigned to hotplugged PCI devices on some IBM systems. The resource mis-allocation not only makes the PCI device unuseable but often makes the entire system unuseable due to resulting machine checks. The hotplug capable PCI slots on the affected systems are not located under a standard P2P bridge but are instead located under PCI root bridges or subtractive decode P2P bridges. For example, the IBM x3850 contains 2 hotplug capable PCI-X slots and 4 hotplug capable PCIe slots with the PCI-X slots each located under a PCI root bridge and the PCIe slots each located under a subtractive decode P2P bridge. The current i386/x86_64 PCI resource allocation code does not use _CRS returned resource information. No other resource information source is available for slots that are not below a standard P2P bridge so incorrect ranges are being allocated from e820 hole causing the bad result. This patch causes the kernel to use _CRS returned resource info. It is roughly based on a change provided by Matthew Wilcox for the ia64 kernel in 2005. Due to possible buggy BIOS factor and possible yet to be discovered kernel issues the function is disabled by default and can be enabled with pci=use_crs. Signed-off-by:
Gary Hade <gary.hade@us.ibm.com> Signed-off-by:
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Gary Hade authored
Avoid creating P2P prefetch window for expansion ROMs Because of the future possibility that P2P prefetch windows will contain address ranges above 4GB some BIOSes are providing space in the P2P non-prefetch windows for expansion ROMs. This is due to expansion ROM BAR 32-bit limitation. When expansion ROM BARs without BIOS assigned address(es) are currently found behind a P2P bridge, the kernel attempts to create a P2P prefetch window for them even though space for them has already been provided in the non-prefetch window. _CRS on some systems with certain resource conservation conscious BIOSes may not provide the extra 1MB or more memory resource needed for the expansion ROM motivated prefetch window causing resource allocation errors. This change corrects the problem by removing IORESOURCE_PREFETCH from the expansion ROM flags initialization. It also removes IORESOURCE_CACHEABLE which seems inappropriate if only non-cacheable memory is available. Signed-off-by:
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Gary Hade authored
Skip ISA ioresource alignment on some systems To conserve limited PCI i/o resource on some IBM multi-node systems, the BIOS allocates (via _CRS) and expects the kernel to use addresses in ranges currently excluded by pcibios_align_resource() [i386/pci/i386.c]. This change allows the kernel to use the currently excluded address ranges on the IBM x3800, x3850, and x3950. Signed-off-by:
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Gary Hade authored
Remove transparent bridge sizing. Due to code in pci_read_bridge_bases() [drivers/pci/probe.c] the child bus of a transparent bridge already has access to the parent bus resources so transparent bridge sizing appears unnecessary. The bridge sizing includes alignment and granularity adjustments that can cause significantly more memory to be reserved from the parant bus than required by devices on the child bus and allotted by _CRS. Signed-off-by:
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David Rientjes authored
When a /proc/bus/pci file is written to, the size of that PCI device's configuration space must be written to the inode. Otherwise, it is possible for the file to specify a size of 0 on stat if a task is holding the same file open. Signed-off-by:
David Rientjes <rientjes@google.com> Signed-off-by:
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David Rientjes authored
On pci_proc_attach_device(), the size of the PCI configuration space is stored in the proc_dir_entry as the size of the file. Thus, the procfs interface to PCI devices should use it instead of the device directly. Signed-off-by:
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Randy Dunlap authored
For cases in which CONFIG_PCIEAER=y (such as distro kernels), allow users to disable PCIE Advanced Error Reporting by using "pci=noaer" on the kernel command line. This can be used to work around hardware or (kernel) software problems. Signed-off-by:
Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by:
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Yoichi Yuasa authored
I got the following error on MIPS Cobalt. PCI: Unable to reserve I/O region #1:8@f00001f0 for device 0000:00:09.1 pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) PCI: Unable to reserve I/O region #3:8@f0000170 for device 0000:00:09.1 pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) pata_via 0000:00:09.1: no available native port The legacy mode IDE resources set the following order. pci_setup_device() Legacy mode ATA controllers have fixed addresses. IDE resources: 0x1F0-0x1F7, 0x3F6, 0x170-0x177, 0x376 | V pcibios_fixup_bus() MIPS Cobalt PCI bus regions have the -0x10000000 offset from PCI resources. pcibios_fixup_bus() fix PCI bus regions. 0x1F0 - 0x10000000 = 0xF00001F0 | V ata_pci_init_one() PCI: Unable to reserve I/O region #1:8@f00001f0 for device 0000:00:09.1 In some architectures, PCI bus regions have the offset from PCI resources. For this reason, pci_setup_device() should set PCI bus regions to dev->resource[]. [akpm@linux-foundation.org: use struct initialiser] Signed-off-by:Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Greg KH <greg@kroah.com> Cc: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Roland Dreier authored
While reading the MSI code trying to find a reason why MSI wouldn't work for devices that have a 32-bit MSI address capability, I noticed that read_msi_msg() seems to read the message data from the wrong offset in this case. Signed-off-by:
Roland Dreier <roland@digitalvampire.org> Acked-by:
Eric W. Biederman <ebiederm@xmission.com> Cc: stable <stable@kernel.org> Signed-off-by:
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Michael Ellerman authored
The code for dynamically assigning new ids to PCI drivers, store_new_id(), calls list_add_tail() with the list head and new node arguments in reversed order. The result is that every new id written essentially overwrites the previous list of ids. Caught with the help of Rusty's "horribly bad" list_node patch: http://lkml.org/lkml/2007/6/10/10Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
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Juha Laiho authored
Force PCI bus renumbering for Compaq EVO N800c laptop, in order to get the cardbus slot recognised. Signed-off-by:
Juha Laiho <Juha.Laiho@iki.fi> Signed-off-by:
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Michael Ellerman authored
The MSI vector reservation system described in Documentation/MSI-HOWTO.txt was removed by Eric in 92db6d10. Remove the references to it in the documentation. While we're here § 5.5.1 refers to x86 hardware requirements, so make that clear. Signed-off-by:
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Johannes Goecke authored
On the "MSI K8T Neo2-FIR" board the BIOS disables the onboard soundcard, if a second PCI soundcard is present. This patch sets the korrect register bit to enable the onboard sound. Removed old code in /drivers/pci/quirks.c that only checks for the PCI-ID and fires on any Board with VIA 8237. New code in /arch/i386/pci/fixup.c checks the DMI-tables and only runs on the specific board. Signed-off-by:
Johannes Goecke <goecke@upb.de> Acked-by:
Jean Delvare <khali@linux-fr.org> Signed-off-by:
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Auke Kok authored
Signed-off-by:
Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by:
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Auke Kok authored
Signed-off-by:
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Auke Kok authored
While PCI_CLASS_REVISION and PCI_REVISION_ID are identical, the code here discards the revision content and is only interested in the class number. Signed-off-by:
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Alex Chiang authored
These IDs are in pciutils, but haven't been added to the kernel yet. Signed-off-by:
Alex Chiang <achiang@hp.com> Signed-off-by:
Matthew Wilcox <matthew@wil.cx> Signed-off-by:
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Thomas Backlund authored
Add support for PicoPower PT86C523 IRQ router to be used with the in-kernel yenta driver for CardBus. With this patch cardbus works on e.g. Dell Latitude XPi P150CD. Initial patch for kernel 2.4 series by Sune Mølgaard http://molgaard.org/code/linux-2.4.31-picopower.patch Ported to 2.6.20 by Chmouel Boudjnah (http://www.chmouel.com) Testing and confirmation that it works by Austin Acton Cleaned up a little for inclusion in a 2.6.21-rc7 based kernel. Added some more cleanups according to CodingStyle, as noted by Randy Dunlap on LKML. [akpm@linux-foundation.org: build fixes] Signed-off-by:
Thomas Backlund <tmb@mandriva.org> Cc: Andi Kleen <ak@suse.de> Signed-off-by:
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Denis V. Lunev authored
The following calltrace is possible now: handle_sysrq machine_emergency_restart mach_reboot_fixups pci_get_device pci_get_subsys down_read The patch skips reboot fixup if called from sysrq-B code. Signed-off-by:Denis V. Lunev <den@openvz.org> Signed-off-by:
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David Brownell authored
On at least ARM (and I'm told MIPS too) dma_free_coherent() has a newish call context requirement: unlike its dma_alloc_coherent() sibling, it may not be called with IRQs disabled. (This was new behavior on ARM as of late 2005, caused by ARM SMP updates.) This little surprise can be annoyingly driver-visible. Since it looks like that restriction won't be removed, this patch changes the definition of the API to include that requirement. Also, to help catch nonportable drivers, it updates the x86 and swiotlb versions to include the relevant warnings. (I already observed that it trips on the bus_reset_tasklet of the new firewire_ohci driver.) Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net> Cc: David Miller <davem@davemloft.net> Acked-by:
Russell King <rmk@arm.linux.org.uk> Cc: Andi Kleen <ak@suse.de> Signed-off-by:
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Christoph Hellwig authored
Signed-off-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by:
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Kristen Carlson Accardi authored
Convert ibmphp to new kthread api Signed-off-by:
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vignesh babu authored
Replacing n & (n - 1) for power of 2 check by is_power_of_2(n) Signed-off-by:
vignesh babu <vignesh.babu@wipro.com> Signed-off-by:
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Kenji Kaneshige authored
Minor cleanups for pciehp_hpc.c. The 80 column rules, removing unnecessary lines, and so on. Signed-off-by:
Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by:
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Kenji Kaneshige authored
Remove trailing whitespaces from pciehp_pci.c. Signed-off-by:
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Kenji Kaneshige authored
Remove trailing whitespaces from pciehp_ctrl.c. Signed-off-by:
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Kenji Kaneshige authored
Remove trailing whitespaces from pciehp_core.c. Signed-off-by:
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Kenji Kaneshige authored
Remove trailing whitespaces from pciehp_hpc.c. Signed-off-by:
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Kenji Kaneshige authored
This patch removes DBG_ENTER_ROUTIN, DBG_LEAVE_ROUTINE and related code, which seem no longer needed. Signed-off-by:
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Kristen Carlson Accardi authored
According to the PCI firmware spec (3.0), the OS must claim control over the PCI Express Capability bits in addition to the PCI Express Native Hot Plug feature when executing _OSC. Signed-off-by:
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Kristen Carlson Accardi authored
When removing a device with a bridge on it, only read the bridge control register if the adapter is actually present. Signed-off-by:
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Kenji Kaneshige authored
Remove unnecessary CONFIG_HOTPLUG_PCI_PCIE_EVENT_MODE. The CONFIG_HOTPLUG_PCI_PCIE_POLL_EVENT_MODE option is not needed because polling mechanism can be enabled through 'pciehp_poll_mode' module option. Signed-off-by:
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Mariusz Kozlowski authored
drivers/pci/hotplug/cpqphp_ctrl.c | 79698 -> 79638 (-60 bytes) drivers/pci/hotplug/cpqphp_ctrl.o | 192896 -> 192736 (-160 bytes) Signed-off-by:
Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by:
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Al Viro authored
Signed-off-by:
Al Viro <viro@zeniv.linux.org.uk> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Linus Torvalds authored
* 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6: [ZLIB]: Fix external builds of zlib_inflate code. [TG3]: Fix APE induced regression [SKY2]: version 1.19 [SKY2]: use netdevice stats struct [SKY2]: fiber advertise bits initialization (trivial) [SKY2]: fix power settings on Yukon XL [SKY2]: ethtool register reserved area blackout
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Al Viro authored
Signed-off-by:
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David S. Miller authored
Move zlib_inflate_blob() out into it's own source file, infutil.c, so that things like the powerpc zImage builder in arch/powerpc/boot/Makefile don't end up trying to compile it. Signed-off-by:David S. Miller <davem@davemloft.net>
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Matt Carlson authored
This patch fixes a bug caused by the recent APE support added for 5761 devices. Signed-off-by:
Matt Carlson <mcarlson@broadcom.com> Signed-off-by:
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