- 28 May, 2020 2 commits
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Will Deacon authored
Merge branches 'for-next/acpi', 'for-next/bpf', 'for-next/cpufeature', 'for-next/docs', 'for-next/kconfig', 'for-next/misc', 'for-next/perf', 'for-next/ptr-auth', 'for-next/sdei', 'for-next/smccc' and 'for-next/vdso' into for-next/core ACPI and IORT updates (Lorenzo Pieralisi) * for-next/acpi: ACPI/IORT: Remove the unused __get_pci_rid() ACPI/IORT: Fix PMCG node single ID mapping handling ACPI: IORT: Add comments for not calling acpi_put_table() ACPI: GTDT: Put GTDT table after parsing ACPI: IORT: Add extra message "applying workaround" for off-by-1 issue ACPI/IORT: work around num_ids ambiguity Revert "ACPI/IORT: Fix 'Number of IDs' handling in iort_id_map()" ACPI/IORT: take _DMA methods into account for named components BPF JIT optimisations for immediate value generation (Luke Nelson) * for-next/bpf: bpf, arm64: Optimize ADD,SUB,JMP BPF_K using arm64 add/sub immediates bpf, arm64: Optimize AND,OR,XOR,JSET BPF_K using arm64 logical immediates arm64: insn: Fix two bugs in encoding 32-bit logical immediates Addition of new CPU ID register fields and removal of some benign sanity checks (Anshuman Khandual and others) * for-next/cpufeature: (27 commits) KVM: arm64: Check advertised Stage-2 page size capability arm64/cpufeature: Add get_arm64_ftr_reg_nowarn() arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 context arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register arm64/cpufeature: Add remaining feature bits in ID_PFR0 register arm64/cpufeature: Introduce ID_MMFR5 CPU register arm64/cpufeature: Introduce ID_DFR1 CPU register arm64/cpufeature: Introduce ID_PFR2 CPU register arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register arm64/cpufeature: Drop open encodings while extracting parange arm64/cpufeature: Validate hypervisor capabilities during CPU hotplug arm64: cpufeature: Group indexed system register definitions by name arm64: cpufeature: Extend comment to describe absence of field info arm64: drop duplicate definitions of ID_AA64MMFR0_TGRAN constants arm64: cpufeature: Add an overview comment for the cpufeature framework ... Minor documentation tweaks for silicon errata and booting requirements (Rob Herring and Will Deacon) * for-next/docs: arm64: silicon-errata.rst: Sort the Cortex-A55 entries arm64: docs: Mandate that the I-cache doesn't hold stale kernel text Minor Kconfig cleanups (Geert Uytterhoeven) * for-next/kconfig: arm64: cpufeature: Add "or" to mitigations for multiple errata arm64: Sort vendor-specific errata Miscellaneous updates (Ard Biesheuvel and others) * for-next/misc: arm64: mm: Add asid_gen_match() helper arm64: stacktrace: Factor out some common code into on_stack() arm64: Call debug_traps_init() from trap_init() to help early kgdb arm64: cacheflush: Fix KGDB trap detection arm64/cpuinfo: Move device_initcall() near cpuinfo_regs_init() arm64: kexec_file: print appropriate variable arm: mm: use __pfn_to_section() to get mem_section arm64: Reorder the macro arguments in the copy routines efi/libstub/arm64: align PE/COFF sections to segment alignment KVM: arm64: Drop PTE_S2_MEMATTR_MASK arm64/kernel: Fix range on invalidating dcache for boot page tables arm64: set TEXT_OFFSET to 0x0 in preparation for removing it entirely arm64: lib: Consistently enable crc32 extension arm64/mm: Use phys_to_page() to access pgtable memory arm64: smp: Make cpus_stuck_in_kernel static arm64: entry: remove unneeded semicolon in el1_sync_handler() arm64/kernel: vmlinux.lds: drop redundant discard/keep macros arm64: drop GZFLAGS definition and export arm64: kexec_file: Avoid temp buffer for RNG seed arm64: rename stext to primary_entry Perf PMU driver updates (Tang Bin and others) * for-next/perf: pmu/smmuv3: Clear IRQ affinity hint on device removal drivers/perf: hisi: Permit modular builds of HiSilicon uncore drivers drivers/perf: hisi: Fix typo in events attribute array drivers/perf: arm_spe_pmu: Avoid duplicate printouts drivers/perf: arm_dsu_pmu: Avoid duplicate printouts Pointer authentication updates and support for vmcoreinfo (Amit Daniel Kachhap and Mark Rutland) * for-next/ptr-auth: Documentation/vmcoreinfo: Add documentation for 'KERNELPACMASK' arm64/crash_core: Export KERNELPACMASK in vmcoreinfo arm64: simplify ptrauth initialization arm64: remove ptrauth_keys_install_kernel sync arg SDEI cleanup and non-critical fixes (James Morse and others) * for-next/sdei: firmware: arm_sdei: Document the motivation behind these set_fs() calls firmware: arm_sdei: remove unused interfaces firmware: arm_sdei: Put the SDEI table after using it firmware: arm_sdei: Drop check for /firmware/ node and always register driver SMCCC updates and refactoring (Sudeep Holla) * for-next/smccc: firmware: smccc: Fix missing prototype warning for arm_smccc_version_init firmware: smccc: Add function to fetch SMCCC version firmware: smccc: Refactor SMCCC specific bits into separate file firmware: smccc: Drop smccc_version enum and use ARM_SMCCC_VERSION_1_x instead firmware: smccc: Add the definition for SMCCCv1.2 version/error codes firmware: smccc: Update link to latest SMCCC specification firmware: smccc: Add HAVE_ARM_SMCCC_DISCOVERY to identify SMCCC v1.1 and above vDSO cleanup and non-critical fixes (Mark Rutland and Vincenzo Frascino) * for-next/vdso: arm64: vdso: Add --eh-frame-hdr to ldflags arm64: vdso: use consistent 'map' nomenclature arm64: vdso: use consistent 'abi' nomenclature arm64: vdso: simplify arch_vdso_type ifdeffery arm64: vdso: remove aarch32_vdso_pages[] arm64: vdso: Add '-Bsymbolic' to ldflags
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Marc Zyngier authored
With ARMv8.5-GTG, the hardware (or more likely a hypervisor) can advertise the supported Stage-2 page sizes. Let's check this at boot time. Reviewed-by:
Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by:
Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by:
Marc Zyngier <maz@kernel.org> Signed-off-by:
Will Deacon <will@kernel.org>
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- 27 May, 2020 1 commit
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Anshuman Khandual authored
There is no way to proceed when requested register could not be searched in arm64_ftr_reg[]. Requesting for a non present register would be an error as well. Hence lets just WARN_ON() when search fails in get_arm64_ftr_reg() rather than checking for return value and doing a BUG_ON() instead in some individual callers. But there are also caller instances that dont error out when register search fails. Add a new helper get_arm64_ftr_reg_nowarn() for such cases. Signed-off-by:
Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by:
Catalin Marinas <catalin.marinas@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mark Brown <broonie@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Link: https://lore.kernel.org/r/1590573876-19120-1-git-send-email-anshuman.khandual@arm.comSigned-off-by:
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- 26 May, 2020 1 commit
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Zenghui Yu authored
Since commit bc8648d4 ("ACPI/IORT: Handle PCI aliases properly for IOMMUs"), __get_pci_rid() has become actually unused and can be removed. Signed-off-by:
Zenghui Yu <yuzenghui@huawei.com> Acked-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by:
Hanjun Guo <guohanjun@huawei.com> Link: https://lore.kernel.org/r/20200509093430.1983-1-yuzenghui@huawei.comSigned-off-by:
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- 21 May, 2020 14 commits
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Anshuman Khandual authored
ID_MMFR4_EL1 has been missing in the CPU context (i.e cpuinfo_arm64). This just adds the register along with other required changes. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:
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Anshuman Khandual authored
Enable the following features bits in ID_AA64PFR1 register as per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:
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Anshuman Khandual authored
Enable MPAM and SEL2 features bits in ID_AA64PFR0 register as per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:
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Anshuman Khandual authored
Enable TLB features bit in ID_AA64ISAR0 register as per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:
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Anshuman Khandual authored
Enable all remaining feature bits like EVT, CCIDX, LSM, HPDS, CnP, XNX, SpecSEI in ID_MMFR4 register per ARM DDI 0487F.a. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:
Mark Rutland <mark.rutland@arm.com> Signed-off-by:
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Anshuman Khandual authored
Enable DIT and CSV2 feature bits in ID_PFR0 register as per ARM DDI 0487F.a specification. Except RAS and AMU, all other feature bits are now enabled. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:
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Anshuman Khandual authored
This adds basic building blocks required for ID_MMFR5 CPU register which provides information about the implemented memory model and memory management support in AArch32 state. This is added per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:
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Anshuman Khandual authored
This adds basic building blocks required for ID_DFR1 CPU register which provides top level information about the debug system in AArch32 state. We hide the register from KVM guests, as we don't emulate the 'MTPMU' feature. This is added per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:
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Anshuman Khandual authored
This adds basic building blocks required for ID_PFR2 CPU register which provides information about the AArch32 programmers model which must be interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:
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Anshuman Khandual authored
Double lock feature can have the following possible values. 0b0000 - Double lock implemented 0b1111 - Double lock not implemented But in case of a conflict the safe value should be 0b1111. Hence this must be a signed feature instead. Also change FTR_EXACT to FTR_LOWER_SAFE. While here, fix the erroneous bit width value from 28 to 4. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:
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Anshuman Khandual authored
ID_DFR0 based TraceFilt feature should not be exposed to guests. Hence lets drop it. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:
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Anshuman Khandual authored
ID_ISAR0[31..28] bits are RES0 in ARMv8, Reserved/UNK in ARMv7. Currently these bits get exposed through generic_id_ftr32[] which is not desirable. Hence define an explicit ftr_id_isar0[] array for ID_ISAR0 register where those bits can be hidden. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:
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Jean-Philippe Brucker authored
Add a macro to check if an ASID is from the current generation, since a subsequent patch will introduce a third user for this test. Signed-off-by:
Jean-Philippe Brucker <jean-philippe@linaro.org> Link: https://lore.kernel.org/r/20200519175502.2504091-6-jean-philippe@linaro.orgSigned-off-by:
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Sudeep Holla authored
Commit f2ae9706 ("firmware: smccc: Refactor SMCCC specific bits into separate file") introduced the following build warning: drivers/firmware/smccc/smccc.c:14:13: warning: no previous prototype for function 'arm_smccc_version_init' [-Wmissing-prototypes] void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit) ^~~~~~~~~~~~~~~~~~~~~~ Fix the same by adding the missing prototype in arm-smccc.h Reported-by:
kbuild test robot <lkp@intel.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com> Link: https://lore.kernel.org/r/20200521110836.57252-1-sudeep.holla@arm.comSigned-off-by:
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- 20 May, 2020 12 commits
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Sudeep Holla authored
For backward compatibility reasons, PSCI maintains SMCCC version as SMCCC didn't provide ARM_SMCCC_VERSION_FUNC_ID until v1.1. PSCI initialises both the SMCCC version and conduit. Similar to the conduit, let us provide accessors to fetch the SMCCC version also so that other SMCCC v1.1+ features can use it. Signed-off-by:
Etienne Carriere <etienne.carriere@st.com> Reviewed-by:
Steven Price <steven.price@arm.com> Reviewed-by:
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Sudeep Holla authored
In order to add newer SMCCC v1.1+ functionality and to avoid cluttering PSCI firmware driver with SMCCC bits, let us move the SMCCC specific details under drivers/firmware/smccc/smccc.c We can also drop conduit and smccc_version from psci_operations structure as SMCCC was the sole user and now it maintains those. No functionality change in this patch though. Signed-off-by:
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Sudeep Holla authored
Instead of maintaining 2 sets of enums/macros for tracking SMCCC version, let us drop smccc_version enum and use ARM_SMCCC_VERSION_1_x directly instead. This is in preparation to drop smccc_version here and move it separately under drivers/firmware/smccc. Signed-off-by:
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Sudeep Holla authored
Add the definition for SMCCC v1.2 version and new error code added. While at it, also add a note that ARM DEN 0070A is deprecated and is now merged into the main SMCCC specification(ARM DEN 0028C). Signed-off-by:
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Sudeep Holla authored
The current link gets redirected to the revision B published in November 2016 though it actually points to the original revision A published in June 2013. Let us update the link to point to the latest version, so that it doesn't get stale anytime soon. Currently it points to v1.2 published in March 2020(i.e. DEN0028C). Signed-off-by:
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Sudeep Holla authored
SMCCC v1.0 lacked discoverability of version and features. To accelerate adoption of few mitigations and protect systems more rapidly from various vulnerability, PSCI v1.0 was updated to add SMCCC discovery mechanism though the PSCI firmware implementation of PSCI_FEATURES(SMCCC_VERSION) which returns success on firmware compliant to SMCCC v1.1 and above. This inturn makes SMCCC v1.1 and above dependent on ARM_PSCI_FW for backward compatibility. Let us introduce a new hidden config for the same to build more features on top of SMCCC v1.1 and above. While at it, also sort alphabetically the psci entry. Signed-off-by:
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Tuan Phan authored
An IORT PMCG node can have no ID mapping if its overflow interrupt is wire based therefore the code that parses the PMCG node can not assume the node will always have a single mapping present at index 0. Fix iort_get_id_mapping_index() by checking for an overflow interrupt and mapping count. Fixes: 24e51604 ("ACPI/IORT: Add support for PMCG") Signed-off-by:
Tuan Phan <tuanphan@os.amperecomputing.com> Reviewed-by:
Hanjun Guo <guoahanjun@huawei.com> Acked-by:
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Anshuman Khandual authored
Currently there are multiple instances of parange feature width mask open encodings while fetching it's value. Even the width mask value (0x7) itself is not accurate. It should be (0xf) per ID_AA64MMFR0_EL1.PARange[3:0] as in ARM ARM (0487F.a). Replace them with cpuid_feature_extract_unsigned_field() which can extract given standard feature (4 bits width i.e 0xf mask) field. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: James Morse <james.morse@arm.com> Cc: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
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Anshuman Khandual authored
This validates hypervisor capabilities like VMID width, IPA range for any hot plug CPU against system finalized values. KVM's view of the IPA space is used while allowing a given CPU to come up. While here, it factors out get_vmid_bits() for general use. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.cs.columbia.edu Cc: linux-kernel@vger.kernel.org Suggested-by:
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James Morse authored
The SDEI handler save/restores the addr_limit using set_fs(). It isn't very clear why. The reason is to mirror the arch code's entry assembly. The arch code does this because perf may access user-space, and inheriting the addr_limit may be a problem. Add a comment explaining why this is here. Suggested-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
James Morse <james.morse@arm.com> Link: https://bugs.chromium.org/p/project-zero/issues/detail?id=822 Link: https://lore.kernel.org/r/20200519182108.13693-4-james.morse@arm.comSigned-off-by:
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Christoph Hellwig authored
The export symbols to register/unregister and enable/disable events aren't used upstream, remove them. [ dropped the parts of Christoph's patch that made the API static too ] Signed-off-by:
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Hanjun Guo authored
The acpi_get_table() should be coupled with acpi_put_table() if the mapped table is not used for runtime after the initialization to release the table mapping, put the SDEI table after using it. Signed-off-by:
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- 18 May, 2020 6 commits
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Jean-Philippe Brucker authored
Currently when trying to remove the SMMUv3 PMU module we get a WARN_ON_ONCE from free_irq(), because the affinity hint set during probe hasn't been properly cleared. [ 238.878383] WARNING: CPU: 0 PID: 175 at kernel/irq/manage.c:1744 free_irq+0x324/0x358 ... [ 238.897263] Call trace: [ 238.897998] free_irq+0x324/0x358 [ 238.898792] devm_irq_release+0x18/0x28 [ 238.899189] release_nodes+0x1b0/0x228 [ 238.899984] devres_release_all+0x38/0x60 [ 238.900779] device_release_driver_internal+0x10c/0x1d0 [ 238.901574] driver_detach+0x50/0xe0 [ 238.902368] bus_remove_driver+0x5c/0xd8 [ 238.903448] driver_unregister+0x30/0x60 [ 238.903958] platform_driver_unregister+0x14/0x20 [ 238.905075] arm_smmu_pmu_exit+0x1c/0xecc [arm_smmuv3_pmu] [ 238.905547] __arm64_sys_delete_module+0x14c/0x260 [ 238.906342] el0_svc_common.constprop.0+0x74/0x178 [ 238.907355] do_el0_svc+0x24/0x90 [ 238.907932] el0_sync_handler+0x11c/0x198 [ 238.908979] el0_sync+0x158/0x180 Just like the other perf drivers, clear the affinity hint before releasing the device. Fixes: 7d839b4b ("perf/smmuv3: Add arm64 smmuv3 pmu driver") Signed-off-by:
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Zhou Wang authored
This patch lets HiSilicon uncore PMU driver can be built as modules. A common module and three specific uncore PMU driver modules will be built. Export necessary functions in hisi_uncore_pmu module, and change irq_set_affinity to irq_set_affinity_hint to pass compile. Signed-off-by:
Zhou Wang <wangzhou1@hisilicon.com> Tested-by:
Qi Liu <liuqi115@huawei.com> Reviewed-by:
Shaokun Zhang <zhangshaokun@hisilicon.com> Link: https://lore.kernel.org/r/1588820305-174479-1-git-send-email-wangzhou1@hisilicon.comSigned-off-by:
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Hanjun Guo authored
The iort_table will be used at runtime after acpi_iort_init(), so add some comments to clarify this to make it less confusing. Signed-off-by:
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Hanjun Guo authored
The mapped GTDT table needs to be released after the driver init. Signed-off-by:
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Yunfeng Ye authored
There are some common codes for stack checking, so factors it out into the function on_stack(). No functional change. Signed-off-by:
Yunfeng Ye <yeyunfeng@huawei.com> Link: https://lore.kernel.org/r/07b3b0e6-3f58-4fed-07ea-7d17b7508948@huawei.comSigned-off-by:
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Douglas Anderson authored
A new kgdb feature will soon land (kgdb_earlycon) that lets us run kgdb much earlier. In order for everything to work properly it's important that the break hook is setup by the time we process "kgdbwait". Right now the break hook is setup in debug_traps_init() and that's called from arch_initcall(). That's a bit too late since kgdb_earlycon really needs things to be setup by the time the system calls dbg_late_init(). We could fix this by adding call_break_hook() into early_brk64() and that works fine. However, it's a little ugly. Instead, let's just add a call to debug_traps_init() straight from trap_init(). There's already a documented dependency between trap_init() and debug_traps_init() and this makes the dependency more obvious rather than just relying on a comment. NOTE: this solution isn't early enough to let us select the "ARCH_HAS_EARLY_DEBUG" KConfig option that is introduced by the kgdb_earlycon patch series. That would only be set if we could do breakpoints when early params are parsed. This patch only enables "late early" breakpoints, AKA breakpoints when dbg_late_init() is called. It's expected that this should be fine for most people. It should also be noted that if you crash you can still end up in kgdb earlier than debug_traps_init(). Since you don't need breakpoints to debug a crash that's fine. Suggested-by:
Douglas Anderson <dianders@chromium.org> Acked-by:
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- 12 May, 2020 1 commit
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Geert Uytterhoeven authored
Several actions are not mitigations for a single erratum, but for multiple errata. However, printing a line like CPU features: detected: ARM errata 1165522, 1530923 may give the false impression that all three listed errata have been detected. This can confuse the user, who may think his Cortex-A55 is suddenly affected by a Cortex-A76 erratum. Add "or" to all descriptions for mitigations for multiple errata, to make it clear that only one or more of the errata printed are applicable, and not necessarily all of them. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200512145255.5520-1-geert+renesas@glider.beSigned-off-by:
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- 11 May, 2020 3 commits
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Hanjun Guo authored
As we already applied a workaround for the off-by-1 issue, it's good to add extra message "applying workaround" to make people less uneasy to see FW_BUG message in the boot log. Signed-off-by:
Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/1588910198-8348-1-git-send-email-guohanjun@huawei.comSigned-off-by:
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Amit Daniel Kachhap authored
Add documentation for KERNELPACMASK variable being added to the vmcoreinfo. It indicates the PAC bits mask information of signed kernel pointers if Armv8.3-A Pointer Authentication feature is present. Signed-off-by:
Amit Daniel Kachhap <amit.kachhap@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Dave Young <dyoung@redhat.com> Cc: Baoquan He <bhe@redhat.com> Link: https://lore.kernel.org/r/1589202116-18265-2-git-send-email-amit.kachhap@arm.comSigned-off-by:
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Amit Daniel Kachhap authored
Recently arm64 linux kernel added support for Armv8.3-A Pointer Authentication feature. If this feature is enabled in the kernel and the hardware supports address authentication then the return addresses are signed and stored in the stack to prevent ROP kind of attack. Kdump tool will now dump the kernel with signed lr values in the stack. Any user analysis tool for this kernel dump may need the kernel pac mask information in vmcoreinfo to generate the correct return address for stacktrace purpose as well as to resolve the symbol name. This patch is similar to commit ec6e822d ("arm64: expose user PAC bit positions via ptrace") which exposes pac mask information via ptrace interfaces. The config gaurd ARM64_PTR_AUTH is removed form asm/compiler.h so macros like ptrauth_kernel_pac_mask can be used ungaurded. This config protection is confusing as the pointer authentication feature may be missing at runtime even though this config is present. Signed-off-by:
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