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- 21 Mar, 2017 2 commits
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Geert Uytterhoeven authored
Somehow the QSPI and SCIF_CLK fragments were inserted at the wrong positions. Restore sort order (alphabetically, per group). Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven authored
Fix typos in hscif2_clk_b_mux[] and hscif4_ctrl_mux[]. Fixes: a56069c4 ("pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 27 Dec, 2016 1 commit
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Niklas Söderlund authored
There are pins on the r8a7795 which are not part of a GPIO bank nor can be muxed between different functions. They do however allow for the bias to be configured. Add those pins to the list of pins and to the bias configuration array. The pins can now be referred to in DT by function names and their bias setting set. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 16 Nov, 2016 5 commits
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Niklas Söderlund authored
Group the QSPI0 and QSPI1 pins into similar groups found in other sh-pfc drivers. The pins can not be muxed between functions other than QSPI, but their drive strength can be controlled. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Niklas Söderlund authored
Group the AVB pins into similar groups found in other sh-pfc drivers. The pins can not be muxed between functions other then AVB but their drive strength can be controlled. The group avb_mdc containing ADV_MDC and ADV_MDIO are on other SoCs called avb_mdio. In pfc-r8a7795 the avb_mdc group already existed and is in use in DT. Therefore add the ADV_MDIO pin to the existing group instead of renaming it. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Niklas Söderlund authored
There are pins on the r8a7795 which are not part of a GPIO bank nor can be muxed between different functions. They do however allow for the drive-strength to be configured. Add those pins to the list of pins and to the drive-strength configuration registers. The pins can now be referred to in DT by function names and their drive-strength modified. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Niklas Söderlund authored
There is a bug in the r8a7795 bias code where a WARN() is trigged anytime a pin from PUEN0/PUD0 is accessed. # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8 [..] Call trace: [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8 [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270 [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30 [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188 [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98 [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128 [<ffff0000081fe3bc>] seq_read+0x16c/0x420 [<ffff00000831a110>] full_proxy_read+0x58/0x88 [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8 [<ffff0000081d8874>] vfs_read+0x84/0x148 [<ffff0000081d9d64>] SyS_read+0x44/0xa0 [<ffff000008082f4c>] __sys_trace_return+0x0/0x4 This is due to the WARN() check if the reg field of the pullups struct is zero, and this should be 0 for pins controlled by the PUEN0/PUD0 registers since PU0 is defined as 0. Change the data structure and use the generic sh_pfc_pin_to_bias_info() function to get the register offset and bit information. Fixes: 56065524 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support") Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Niklas Söderlund authored
The last else statement is missing braces, and the indentation level can be reduced. Suggested-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 16 Aug, 2016 1 commit
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Laurent Pinchart authored
Only the DU parallel RGB output signals are included, HDMI and TCON pins will be added in separate groups. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 08 Aug, 2016 2 commits
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Geert Uytterhoeven authored
This source file handles r8a7795 only, which is not the sole member of the R-Car Gen3 family. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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Ulrich Hecht authored
Implements pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 23 Jun, 2016 2 commits
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Ramesh Shanmugasundaram authored
This patch adds DRIF[0-3] pinmux support for r8a7795 SoC. Signed-off-by:
Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Kuninori Morimoto authored
Now we have PINMUX_SINGLE(). Let's use it instead of PINMUX_IPSR_NOGP() Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 10 Jun, 2016 1 commit
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Wolfram Sang authored
Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 29 Mar, 2016 1 commit
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Laurent Pinchart authored
Define the drive strength registers for the R8A7795. As the PFC driver for the SoC only defines GPIO pins at the moment, limit drive strength support to those pins. Pins without GPIO capabilities will be supported later. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 26 Feb, 2016 2 commits
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Ramesh Shanmugasundaram authored
This patch adds CANFD[0-1] pinmux support to r8a7795 SoC. Signed-off-by:
Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Ramesh Shanmugasundaram authored
This patch adds CAN[0-1] pinmux support to r8a7795 SoC. Signed-off-by:
Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 18 Feb, 2016 2 commits
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Takeshi Kihara authored
This patch adds PWM[0-6] pinmux support to r8a7795 SoC. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: adapted to mainline PFC driver] Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Magnus Damm authored
Most pins on the r8a7795 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". Tested on r8a7795 Salvator-X with an external loop back adapter on EXIO_D that connects pin 9 (IRQ2/GP2_02) and pin 26 (ExA22/GP2_06). Signed-off-by:
Magnus Damm <damm+renesas@opensource.se> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 08 Feb, 2016 4 commits
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Takeshi Kihara authored
This patch adds USB[0-2] (USB2.0 host) pinmux support to r8a7795 SoC. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven authored
Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet. This has no user-visible impact, as the definitions were not really used. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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Geert Uytterhoeven authored
Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet. This has no user-visible impact, as the string used for configuration ("ssi01239_ctrl") was already correct. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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Geert Uytterhoeven authored
This macro describes a pinmux configuration that needs configuration in both a Peripheral Function Select Register (IPSR) and in a GPIO/Peripheral Function Select Register 1 (GPSR). Reflect that in the macro name for clarity. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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- 16 Dec, 2015 2 commits
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Takeshi Kihara authored
This patch adds SATA0 pinmux support to r8a7795 SoC. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: adjusted for new PFC driver] Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Takeshi Kihara authored
Add SDHI[0-3] pinmux support to r8a7795 SoC. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Dirk Behme <dirk.behme@gmail.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 08 Dec, 2015 3 commits
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Geert Uytterhoeven authored
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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Geert Uytterhoeven authored
Extracted from a big patch by Takeshi Kihara. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Correct MSIOF3 TXD_A/RXD_A pins] Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven authored
Pins that (1) can be configured as either GPIO or a single peripheral function, and (2) that don't need configuration in an IPSRx register, should still be listed in the pinmux_data[] array. Else selecting the peripheral function fails with e.g.: sh-pfc e6060000.pfc: cannot locate data/mark enum_id for mark 1281 (mark 1281 is MSIOF0_SCK_MARK). Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 30 Nov, 2015 4 commits
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Kuninori Morimoto authored
Many SoC needs each PORT_GP_x() macros, but we can share/reuse same one. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven authored
Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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Geert Uytterhoeven authored
Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet. This has no user-visible impact. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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Geert Uytterhoeven authored
On r8a7795, PORT_GP_x() is a macro for defining GPIOs 0..x. In all other sh-pfc code, PORT_GP_x() is a macro for defining GPIOs 0..(x-1). Make the r8a7795 macro definitions consistent with the rest of the sh-pfc codebase. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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- 20 Oct, 2015 2 commits
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Geert Uytterhoeven authored
This header file will be removed soon. Copy the helper macro RCAR_GP_PIN(), which is used by the pinctrl drivers only, to sh_pfc.h, and drop the #include. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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Geert Uytterhoeven authored
The sh_pfc_soc_info.gpio_data[] array contains not only GPIO data, but also various other pinmux-related data (functions and marks). Every single driver already calls its local array pinmux_data[]. Hence rename the sh_pfc_soc_info member to "pinmux_data". Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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- 02 Oct, 2015 6 commits
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Takeshi Kihara authored
This patch adds EthernetAVB Based on a much lager patch by Takeshi Kihara which was originally posted by Kuninori Morimoto. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [horms: extracted from a larger patch; corrected swapped {MATCH,CAPTURE_A} pins] Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Kuninori Morimoto authored
Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Kuninori Morimoto authored
Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Kuninori Morimoto authored
Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven authored
This patch adds SCIF0/1/2/3/4/5 Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> [Morimoto-san: Updated] Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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Takeshi Kihara authored
Add PFC base support for the R8A7795 SoC. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> [Morimoto-san: updated] Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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