- 30 Jul, 2018 17 commits
-
-
Arnd Bergmann authored
All users of do_gettimeofday() have been removed, but this one recently crept in, along with an incorrect printing of the microseconds portion. This converts it to using ktime_get_real_timespec64() as a direct replacement, and adds the leading zeroes. I considered using monotonic times (ktime_get()) instead, but as this timestamp appears to only be used for humans rather than compared with other timestamps, the real time domain is probably good enough. Fixes: e43b045e2c82 ("drm/msm/gpu: Capture the state of the GPU") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Rob Clark <robdclark@gmail.com>
-
Sean Paul authored
This fixes up a collision between introducing dual-channel support and the dsi refactors. This patch applies the same dual-channel considerations and pclk calculations to both v2 and 6G, with a bit of abstracting for good measure. Signed-off-by:
Sean Paul <seanpaul@chromium.org> Signed-off-by:
-
Sean Paul authored
In these cases, we want to enumerate _all_ clocks, not just the ones that are assigned a rate. Signed-off-by:
-
Sean Paul authored
Should work with the legacy handling in of, but we shouldn't rely on that. Signed-off-by:
-
Jordan Crouse authored
For hangs, dump copy out the contents of the buffer objects attached to the guilty submission and print them in the crash dump report. Signed-off-by:
Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by:
-
Jordan Crouse authored
HLSQ, SP and TP registers are only accessible from a special aperture and to make matters worse the aperture is blocked from the CPU on targets that can support secure rendering. Luckily the GPU hardware has its own purpose built register dumper that can access the registers from the aperture. Add a5xx specific code to program the crashdumper and retrieve the wayward registers and dump them for the crash state. Also, remove a block of registers the regular CPU accessible list that aren't useful for debug which helps reduce the size of the crash state file by a goodly amount. Signed-off-by:
-
Jordan Crouse authored
Add the contents of each ringbuffer to the GPU state and dump the data in the crash file encoded with ascii85. To save space only the used portions of the ringbuffer are dumped. Signed-off-by:
-
Jordan Crouse authored
Convert the format of the 'show' debugfs file and the crash dump to a format resembling YAML. This should be easier to parse and be more flexible for future changes and expansions. v2: Use a standard .rst for the msm crashdump documentation Signed-off-by:
-
Jordan Crouse authored
Capture the GPU state on a GPU hang and store it for later playback via the devcoredump facility. Only one crash state is stored at a time on the assumption that the first hang is usually the most interesting. The existing crash state can be cleared after capturing it and then a new one will be captured on the next hang. Signed-off-by:
-
Jordan Crouse authored
Do a bit of cleanup to prepare for upcoming changes to pass the hanging task comm and cmdline to the crash dump function. v2: Use GFP_ATOMIC while holding the rcu lock per Chris Wilson Signed-off-by:
-
Jordan Crouse authored
Convert the existing GPU show function to use the GPU state to dump the information rather than reading it directly from the hardware. This will require an additional step to capture the state before dumping it for the existing nodes but it will greatly facilitate reusing the same code for dumping a previously captured state from a GPU hang. Signed-off-by:
-
Jordan Crouse authored
Add the infrastructure to capture the current state of the GPU and store it in memory so that it can be dumped later. For now grab the same basic ringbuffer information and registers that are provided by the debugfs 'gpu' node but obviously this should be extended to capture a much larger set of GPU information. Signed-off-by:
-
Jordan Crouse authored
Add a puts function for the coredump printer to bypass printf() for constant strings for a speed boost. Reorganize the coredump printf callback to share as much code as possible. v2: Try to reuse code between print and puts as suggested by Chris Wilson Signed-off-by: -
Jordan Crouse authored
Add a puts() function to use seq_puts() to help speed up up print time for constant strings. Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
-
Jordan Crouse authored
Add drm_puts() for a much faster path to print constant strings into a drm_printer object with memcpy and friends. This can have seconds off of really large outputs such as GPU dumps. If the drm_printer object supports a custom puts function then use that otherwise fall back to the slower legacy printf call. v2: Add documentation for drm_puts() per Daniel Vetter Reviewed-by:
-
Jordan Crouse authored
Add a drm printer suitable for use with the read callback for devcoredump or other suitable buffer based output format that isn't otherwise covered by seq_file. v2: Add improved documentation per Daniel Vetter Signed-off-by:
-
Jordan Crouse authored
The i915 DRM driver very cleverly used ascii85 encoding for their GPU state file. Move the encode functions to a general header file to support other drivers that might be interested in the same functionality. v4: Make the return value const char * as suggested by Chris Wilson v3: Fix error_puts -> err_puts pointed out by the 01.org bot v2: Update API to be cleaner for the caller as suggested by Chris Wilson Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
-
- 26 Jul, 2018 17 commits
-
-
Rajesh Yadav authored
The vblank on/off calls were missing in dpu_crtc leading to "driver forgot to call drm_crtc_vblank_off()" warning while entering suspend state. Also handle the state update completion event for a crtc being disabled in current atomic commit. This patch depends on https://www.spinics.net/lists/dri-devel/msg182402.htmlSigned-off-by:
Rajesh Yadav <ryadav@codeaurora.org> Signed-off-by:
-
Jeykumar Sankaran authored
SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a top level wrapper consisting of Display Processing Unit (DPU) and display peripheral modules such as Display Serial Interface (DSI) and DisplayPort (DP). MDSS functions essentially as a back-end composition engine. It blends video and graphic images stored in the frame buffers and scans out the composed image to a display sink (over DSI/DP). The following diagram represents hardware blocks for a simple pipeline (two planes are present on a given crtc which is connected to a DSI connector): MDSS +---------------------------------+ | +-----------------------------+ | | | DPU | | | | +--------+ +--------+ | | | | | SSPP | | SSPP | | | | | +----+---+ +----+---+ | | | | | | | | | | +----v-----------v---+ | | | | | Layer Mixer (LM) | | | | | +--------------------+ | | | | +--------------------+ | | | | | PingPong (PP) | | | | | +--------------------+ | | | | +--------------------+ | | | | | INTERFACE (VIDEO) | | | | | +---+----------------+ | | | +------|----------------------+ | | | | | +------|---------------------+ | | | | DISPLAY PERIPHERALS | | | | +---v-+ +-----+ | | | | | DSI | | DP | | | | | +-----+ +-----+ | | | +----------------------------+ | +---------------------------------+ The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs) depends on SoC capabilities. Overview of DPU sub-blocks: --------------------------- * Source Surface Processor (SSPP): Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are capable of performing format conversion, scaling and quality improvement for source surfaces. * Layer Mixer (LM): Blend source surfaces together (in requested zorder) * PingPong (PP): This block controls frame done interrupt output, EOL and EOF generation, overflow/underflow control. * Display interface (INTF): Timing generator and interface connecting the display peripherals. DRM components mapping to DPU architecture: ------------------------------------------ PLANEs maps to SSPPs CRTC maps to LMs Encoder maps to PPs, INTFs Data flow setup: --------------- MDSS hardware can support various data flows (e.g.): - Dual pipe: Output from two LMs combined to single display. - Split display: Output from two LMs connected to two separate interfaces. The hardware capabilities determine the number of concurrent data paths possible. Any control path (i.e. pipeline w/i DPU) can be routed to any of the hardware data paths. A given control path can be triggered, flushed and controlled independently. Changes in v3: - Move msm_media_info.h from uapi to dpu/ subdir - Remove preclose callback dpu (it's handled in core) - Fix kbuild warnings with parent_ops - Remove unused functions from dpu_core_irq - Rename mdss_phys to mdss - Rename mdp_phys address space to mdp - Drop _phys from vbif and regdma binding names Signed-off-by:Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by:
Archit Taneja <architt@codeaurora.org> Signed-off-by:
Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by:
Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by:
Sravanthi Kollukuduru <skolluku@codeaurora.org> Signed-off-by:
-
Jeykumar Sankaran authored
Used by the dpu driver for custom suspend/resume. Changes in v3: - None Signed-off-by:
-
Jeykumar Sankaran authored
Called right before wait_for_commit_done() to perform kickoff for active crtcs. Changes in v3: - None Signed-off-by:
-
Jeykumar Sankaran authored
dpu uses these elsewhere in the driver (in addition to increasing MAX_PLANES, that'll come later), so pull them out into #define. Changes in v3: - None Signed-off-by:
-
Jeykumar Sankaran authored
This simplifies cleanup, to make sure nothing drops out in case of error. Changes in v3: - None Signed-off-by:
-
Jeykumar Sankaran authored
Useful for incoming DPU support Changes in v3: - None Signed-off-by:
-
Sean Paul authored
I missed this during the atomic conversion Changes in v3: - None Signed-off-by:
-
Abhinav Kumar authored
Make the pclk_rate u64 to accommodate higher pixel clock rates. Changes in v3: - Converted pclk_rate to u32 (Archit) - Rebase on dsi cleanup set in msm-next Cc: Sibi Sankar <sibis@codeaurora.org> Cc: Archit Taneja <architt@codeaurora.org> Signed-off-by:
-
Jeykumar Sankaran authored
Enable drm core zpos normalization for planes. Changes in v3: - None Signed-off-by:
-
Rajesh Yadav authored
SoCs having mdp5 or dpu have identical tree like device hierarchy where MDSS top level wrapper manages common power resources for all child devices. Subclass msm_mdss so that msm_mdss includes common defines and mdp5/dpu mdss derivations to include any extensions. Add mdss helper interface (msm_mdss_funcs) to msm_mdss base for mdp5/dpu mdss specific implementation calls. This change subclasses msm_mdss for mdp5, dpu specific changes will be done separately. Changes in v3: - Added Archit's R-b Reviewed-by:
-
Sean Paul authored
DPU doesn't use this, so push it into the mdp drivers. Changes in v3: - None Signed-off-by:
-
Abhinav Kumar authored
Currently, DRM bridge for DPU relies on the default video mode setting to set the encoder mode. Add an explicit call to set the encoder mode for bridges. Changes in v3: - None Reviewed-by:
Archit Taneja <architt@codeauorora.org> Signed-off-by:
-
Rajesh Yadav authored
postdiv_lock spinlock was used before initialization for 10nm pll. It causes following spin_bug: "BUG: spinlock bad magic on CPU#0". Initialize spinlock before its usage. Changes in v3: - Added Archit's R-b Reviewed-by:
-
Chandan Uddaraju authored
Current DSI driver uses two connectors for dual DSI case even though we only have one panel. Fix this by implementing one connector/bridge for dual DSI use case. Use master DSI controllers to register one connector/bridge. Changes in v3: - None Reviewed-by:
-
Chandan Uddaraju authored
For dual dsi mode, the horizontal timing needs to be divided by half since both the dsi controllers will be driving this panel. Adjust the pixel clock and DSI timing accordingly. Changes in v3: - Added Archit's R-b - Rebase on dsi cleanup set in msm-next Cc: Sibi Sankar <sibis@codeaurora.org> Reviewed-by:
-
Jeykumar Sankaran authored
Qualcomm Snapdragon chipsets uses compressed format to optimize BW across multiple IP's. This change adds needed modifier support in drm for a simple 4x4 tile based compressed variants of base formats. Changes in v3: - Removed duplicate entry for DRM_FORMAT_MOD_QCOM_COMPRESSED (Rob Clark) Changes in v4: - Remove all modifiers aside from COMPRESSED, this includes tiled and 10-bit Signed-off-by:
-
- 25 Jul, 2018 6 commits
-
-
vkorjani authored
After enabling DSC we need to send compression mode command packet and pps data packet, for which 2 new data types are added 07h Compression Mode Data Type Write , short write, 2 parameters 0Ah PPS Long Write (word count determines number of bytes) This patch adds support to send these packets. Cc: David Airlie <airlied@linux.ie> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org Cc: linux-fbdev@vger.kernel.org Changes in v3: - None Signed-off-by:
vkorjani <vikas.korjani@intel.com> [seanpaul removed pps_write_buffer fn, added types to packet_format helpers] Signed-off-by:
-
Carsten Behling authored
modesetting X11 driver may provide negative x/y cordinates in mdp5_crtc_cursor_move call when rotation is enabled. Cursor buffer can overlap down to its negative width/height. ROI has to be recalculated for negative x/y indicating using the lower/right corner of the cursor buffer and hotspot must be set in MDP5_LM_CURSOR_XY_SRC_Y MDP5_LM_CURSOR_XY_SRC_X. Signed-off-by:
Carsten Behling <carsten.behling@gmail.com> Signed-off-by:
-
Sibi Sankar authored
Replace version checks with the helper functions bound to cfg_handler for DSI v2, DSI 6G 1.x and DSI 6G v2.0+ controllers Signed-off-by:
Sibi Sankar <sibis@codeaurora.org> Signed-off-by:
-
Sibi Sankar authored
Add dsi host helper function implementation for DSI v2 DSI 6G 1.x and DSI 6G v2.0+ controllers Signed-off-by:
-
Sibi Sankar authored
Add dsi host helper functions support for DSI v2 and DSI 6G 1.x controllers that are under version checks Signed-off-by:
-
Rob Clark authored
f9cb8d8d fixed various race conditions with CTL flush, in particular flushing and sending the START signal before encoder state was updated. But it did this a little too well in some cases that don't trigger encoder->enable(), and CTL[n].FLUSH would never be set. When page flips happen it would paper over the bug, since the first plag flip would flush out the state to the hardware. The issue could be reproduced with, for example, modetest (without the '-v' argument). Fixes: f9cb8d8d drm/msm/mdp5: rework CTL START signal handling Signed-off-by:
-
