- 08 May, 2020 1 commit
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Hawking Zhang authored
get_hive_id/get_node_id/get_topology_info/set_topology_info are common xgmi command supported by TA for all the ASICs that support xgmi link. They should be implemented as common helper functions to avoid duplicated code per IP generation Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
John Clements <john.clements@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 07 May, 2020 7 commits
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Chunming Zhou authored
Glad to spend time on kernel driver in past years. I've moved to new focus in umd and couldn't commit enough time to discussions. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Chen Zhou authored
Remove duplicate headers which are included twice. Signed-off-by:
Chen Zhou <chenzhou10@huawei.com> Signed-off-by:
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Jason Yan authored
Fix the following coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c:3216:16-22: Unneeded variable: "result". Return "DC_OK" on line 3229 Signed-off-by:
Jason Yan <yanaijie@huawei.com> Signed-off-by:
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Bernard Zhao authored
There is DEVICE_ATTR mechanism in separate attribute define. So this change is to use attr array, also use sysfs_create_files in init function & sysfs_remove_files in fini function. This maybe make the code a bit readable. Signed-off-by:
Bernard Zhao <bernard@vivo.com> Changes since V1: *Use DEVICE_ATTR mechanism Link for V1: *https://lore.kernel.org/patchwork/patch/1228076/ V2: make array const to fix build errors Reviewed-by:
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Simon Ser authored
This patch adds a basic cursor check when an atomic test-only commit is performed. The position and size of the cursor plane is checked. This should fix user-space relying on atomic checks to assign buffers to planes. Signed-off-by:
Simon Ser <contact@emersion.fr> Reported-by:
Roman Gilg <subdiff@gmail.com> References: https://github.com/emersion/libliftoff/issues/46 Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] We're sending the drm vblank event a frame too early in the case where the pageflip happens close to VUPDATE and ends up blocking the signal. The implementation in DM was previously correct *before* we started sending vblank events from VSTARTUP unconditionally to handle cases where HUBP was off, OTG was ON and userspace was still requesting some DRM planes enabled. As part of that patch series we dropped VUPDATE since it was deemed close enough to VSTARTUP, but there's a key difference betweeen VSTARTUP and VUPDATE - the VUPDATE signal can be blocked if we're holding the pipe lock. There was a fix recently to revert the unconditional behavior for the DCN VSTARTUP vblank event since it was sending the pageflip event on the wrong frame - once again, due to blocking VUPDATE and having the address start scanning out two frames later. The problem with this fix is it didn't update the logic that calls drm_crtc_handle_vblank(), so the timestamps are totally bogus now. [How] Essentially reverts most of the original VSTARTUP series but retains the behavior to send back events when active planes == 0. Some refactoring/cleanup was done to not have duplicated code in both the handlers. Fixes: 16f17eda ("drm/amd/display: Send vblank and user events at vsartup for DCN") Fixes: 3a2ce8d6 ("drm/amd/display: Disable VUpdate interrupt for DCN hardware") Fixes: 2b5aed9a ("drm/amd/display: Fix pageflip event race condition for DCN.") Signed-off-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
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John Clements authored
Invoke sequence should abort when ras interrupt is detected before reading TA host shared memory Reviewed-by:
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- 06 May, 2020 8 commits
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ChenTao authored
Fixes warning because size is uint32_t and can never be negtative drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1296:12: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (size < 0) Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
ChenTao <chentao107@huawei.com> Signed-off-by:
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Felix Kuehling authored
Releasing the AMDGPU BO ref directly leads to problems when BOs were exported as DMA bufs. Releasing the GEM reference makes sure that the AMDGPU/TTM BO is not freed too early. Also take a GEM reference when importing BOs from DMABufs to keep references to imported BOs balances properly. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Tested-by:
Alex Sierra <alex.sierra@amd.com> Acked-by:
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Alex Deucher authored
We set the fb smem pointer to the offset into the BAR, so keep the fbdev bo in vram. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=207581 Fixes: 6c8d74ca ("drm/amdgpu: Enable scatter gather display support") Reviewed-by:
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Evan Quan authored
Since gfxoff should be disabled first before trying to access those GC registers. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
As this is already properly handled in amdgpu_gfx_off_ctrl(). In fact, this unnecessary cancel_delayed_work_sync may leave a small time window for race condition and is dangerous. Signed-off-by:
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Evan Quan authored
Otherwise, MGCG/MGLS will be left enabled. Signed-off-by:
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Christian König authored
This should speed up debugging VRAM access a lot. v2: add HDP flush/invalidate Unrevert: RAS issue at root of the issue has been addressed Signed-off-by:
Jonathan Kim <Jonathan.Kim@amd.com> Signed-off-by:
Kent Russell <kent.russell@amd.com> Acked-by:
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Jerry (Fangzhi) Zuo authored
It works together with drm framework "drm: Add support for DP 1.4 Compliance edid corruption test" Add the edid validity check scenario when edid base block is read back with error. Send back real edid checksum and enable fail-safe mode in DC. Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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- 05 May, 2020 21 commits
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Arnd Bergmann authored
After the structure was padded to 1024 bytes, it is no longer suitable for being a local variable, as the function surpasses the warning limit for 32-bit architectures: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:587:5: error: stack frame size of 1072 bytes in function 'amdgpu_ras_feature_enable' [-Werror,-Wframe-larger-than=] int amdgpu_ras_feature_enable(struct amdgpu_device *adev, ^ Use kzalloc() instead to get it from the heap. Fixes: a0d25482 ("drm/amdgpu: update RAS TA to Host interface") Acked-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Andriy Gapon authored
This uses backlight_device_set_brightness() to set the brightness level requested via ATIF. Signed-off-by:
Andriy Gapon <avg@FreeBSD.org> Signed-off-by:
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ChenTao authored
Fixes warning because pipe is unsigned long and can never be negtative vers/gpu/drm/radeon/radeon_kms.c:831:11: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (pipe < 0 || pipe >= rdev->num_crtc) { drivers/gpu/drm/radeon/radeon_kms.c:857:11: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (pipe < 0 || pipe >= rdev->num_crtc) { Reported-by: -
Nathan Chancellor authored
When building with Clang: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4160:53: warning: overflow in expression; result is -294967296 with type 'long' [-Winteger-overflow] expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4L; ^ 1 warning generated. Multiplication happens first due to order of operations and both NSEC_PER_SEC and 4 are long literals so the expression overflows. To avoid this, make 4 an unsigned long long literal, which matches the type of expires (u64). Fixes: 3f12acc8 ("drm/amdgpu: put the audio codec into suspend state before gpu reset V3") Link: https://github.com/ClangBuiltLinux/linux/issues/1017Signed-off-by:Nathan Chancellor <natechancellor@gmail.com> Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Anthony Koo authored
Add dmub related struct field for future use. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Anthony Koo authored
[Why] Make a separation of what belongs in the differen dmub headers dmub_srv.h is for exposing dmub srv interface to rest of driver. other headers inside dmub/inc exposes cmds and definitions that are owned by the firmware [How] keep firmware owned definitions in dmub/inc move stuff that is purely driver interface headers to dmub/ since those are interface calls that are defined for rest of driver to use Signed-off-by:
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Aurabindo Pillai authored
Signed-off-by:
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Jerry (Fangzhi) Zuo authored
Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Aurabindo Pillai authored
[why] During hotplug, a DP port may be connected to the sink through passive adapter which does not support DPCD reads. Issuing reads without checking for this condition will result in errors [how] Ensure the link is in aux_mode before initiating operation that result in a DPCD read. Signed-off-by:
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Isabel Zhang authored
[Why] Want to make use of detile buffer of all 4 pipes to maximize amount of data stored to hide certain memory latency cases. [How] In case of 1 plane and 1 stream, program 4 pipes to each retrieve 1/4 of plane later mixed together by the MPCs. Added support for transition from 4 to 1 MPC to 2 to 1 MPC or no pipe split case and vice versa. Currently, only enabled if debug flag is set. Signed-off-by:
Isabel Zhang <isabel.zhang@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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yanyan kang authored
[Why] same with CL#1711022(correcting yuv420 black color in function dcn10_blank_pixel_data,program_scaler), yuv420 black color also needs to be correct when enabling HDMI stream at the resume procedure. [How] correcting the yuv420 black color according to the way how 420 is packed :2 channels carry Y component, 1 channel alternate between Cb and Cr. Signed-off-by:
yanyan kang <Yanyan.Kang@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Anthony Koo authored
[Why] For a type like PSR version, it makes sense for most of the code to include a dc type, instead of having this a fw type define since this is a capability and type exposed by dc. Especially if it doesn't even need to communicate with the fw. The code that is packing the firmware command message should be the one who needs to translate the psr version into a command that the firmware understands. [How] Add a dc_psr_version enum. Signed-off-by:
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Stylon Wang authored
[Why] FP16 pixel format is not declared to DRM in Linux DM. [How] Add FP16 format to the support list presented to DRM from Linux DM. Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
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Lewis Huang authored
[Why] in Is_Support function, driver report different caps between same timing but different scaling cause OS inconsistent. [How] min_row_time is a local that’s only used for verifying immediate flip support. Clamp the vratio used for its calculation to 1.0. Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Alvin Lee authored
[Why] For certain display configurations we want to allow PSTATE switch when one display can switch in VACTIVE and the other display can switch in VBLANK [How] Add extra condition to dcn2 pstate support check Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Roman Li authored
[Why] Wait counter is not being reset for each pipe. [How] Move counter reset into pipe loop scope. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
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Aric Cyr authored
[Why] What a mode change is requested for the same timing a full stream reset can occur in some cases which causes monitor to blank for a few seconds. [How] Do not consider infoframe updates as needing a full stream reset as they will be handled on the first flip after a modeset when surface information is available. Signed-off-by:
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Sung Lee authored
[WHY & HOW] There is a problem in hscale_pixel_rate, the bug causes DCN to be more optimistic (more likely to underflow) in upscale cases during prefetch. This commit ports the fix from DV code to address these issues. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Yongqiang Sun authored
[Why] panel_cntl specific register should be access in panel_cntl object. [How] Move these register access from abm to panel_cntl. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Jason Yan authored
Fix the following coccicheck warning: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:1574:5-8: Unneeded variable: "ret". Return "0" on line 1586 Signed-off-by:
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- 01 May, 2020 3 commits
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shaoyunl authored
Create gfx_v10_0_rlc_funcs_sriov for nv12 with rlcg_write function pointers be initialized so driver can use RLCG to write aceess CSIB and CP_ME_CNTL registers when nv12 in sriov mode Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
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Yong Zhao authored
The queue mask used for set_resources always assumes the queue number per pipe is 8, so KFD needs to align with that by using function amdgpu_queue_mask_bit_to_set_resource_bit(). Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Signed-off-by:
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Yong Zhao authored
Rename it to amdgpu_queue_mask_bit_to_set_resource_bit() to be more specific about its functionality. KFD will use it later. Signed-off-by:
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