- 17 Oct, 2019 40 commits
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Tianci.Yin authored
add memory training implementation code to save resume time. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Tianci.Yin authored
memory training using specific fixed vram segment, reserve these segments before anyone may allocate it. Reviewed-by:
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Tianci.Yin authored
add interface for memory training. Reviewed-by:
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Tianci.Yin authored
parse firmware to get memory training capability and fb location. Reviewed-by:
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Tianci.Yin authored
add new vram_reserve_block structure and atomfirmware_internal_constants enumeration Reviewed-by:
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Tianci.Yin authored
introduce psp_v11_0_is_sos_alive func for common use. Reviewed-by:
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Tianci.Yin authored
add a generic helper function for accessing framebuffer via MMIO Reviewed-by:
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Tianci.Yin authored
update amdgpu_discovery to get IP revision. Reviewed-by:
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Prike Liang authored
implement get_power_profile_mode for getting power profile mode status. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
We need to allocate a large enough buffer for the session info, otherwise the IB test can overwrite other memory. - Session info is 128K according to mesa - Use the same session info for create and destroy Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Tested-by:
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Alex Deucher authored
We need to allocate a large enough buffer for the session info, otherwise the IB test can overwrite other memory. v2: - session info is 128K according to mesa - use the same session info for create and destroy Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241Acked-by: -
Alex Deucher authored
We need to allocate a large enough buffer for the session info, otherwise the IB test can overwrite other memory. v2: - session info is 128K according to mesa - use the same session info for create and destroy Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241Acked-by: -
Alex Deucher authored
Add proper config check. Reviewed-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
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YueHaibing authored
Fix sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:746:6: warning: symbol 'dc_link_detect_helper' was not declared. Should it be static? Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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Bhawanpreet Lakha authored
Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
This patch adds handling of dp is usb-c, it is not tested but is needed to support dp over usb-c Signed-off-by:
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Bhawanpreet Lakha authored
Use requested_dispclk_khz / 1000 directly Signed-off-by:
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Lewis Huang authored
[Why] SMU fixed this issue after version 0x370c00 [How] enable smu send message to set dcfclk after smu version 0x370c00 Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Acked-by:
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joseph gravenor authored
[why] Should always MP0_BASE for any register definition from MP per-IP header files. I belive the reason the linux version of MP1_BASE works is The 0th element of the 0th table of that is identical to the corrisponding value of MP0_BASE in the renoir offset header file. The reason we should only use MP0_BASE is There is only one set of per-IP headers MP that includes all register definitions related to SMU IP block. This IP includes MP0, MP1, MP2 and an ecryption engine that can be used only by MP0. As a result all register definitions from MP file should be based only on MP0_BASE data. [How] Change MP1_BASE to MP0_BASE Signed-off-by:
joseph gravenor <joseph.gravenor@amd.com> Acked-by:
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Eric Yang authored
[Why] Handle the case where we don't get a valid table. Also fixes compiler warning for variable potentially used before assignment. [How] If the entire table has no valid fclk, reject the table and use our own hard code. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
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Michael Strauss authored
[WHY] dprefclk is improperly read due to incorrect units used. Causes an audio clock to be improperly set, making audio non-functional and videos play back too fast [HOW] Scale dprefclk value from MHz to KHz (multiply by 1000) to ensure that dprefclk_khz is in correct units Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Acked-by:
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Bhawanpreet Lakha authored
Handle 18 DecimalBPP like other cases Signed-off-by:
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Dmytro Laktyushkin authored
Previously 8k30 worked with dsc and odm combine due to a workaround that ran the formula a second time with dsc support enable should dsc validation fail. This worked when clocks were low enough for formula to enable odm to lower voltage, however now broke due to increased clocks. This change updates the ODM combine policy within the formula to properly reflect our current policy within DC, only enabling ODM when we have to, as well as adding a check for viewport width when dsc is enabled. As a side effect the redundant call to dml when odm is required is now unnecessary. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Sung Lee authored
[Why] Previously only dummy functions were added in Diags for FPGA. On silicon, this would lead to a segmentation fault on silicon diags. [How] Check if diags silicon and if so, add dummy functions. Signed-off-by:
Sung Lee <sung.lee@amd.com> Acked-by:
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Bhawanpreet Lakha authored
DPM level is 8 these were incorrect before. Fix them Signed-off-by:
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Bhawanpreet Lakha authored
The values for bounding box and res_caps were incorrect. So Fix them Signed-off-by:
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Bhawanpreet Lakha authored
use dcn20 common regs define to share some regs with dcn20 Signed-off-by:
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Bhawanpreet Lakha authored
Detile buffer size affects dcc caps, it was already added for dcn2. Now add it for dcn21 Signed-off-by:
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Dmytro Laktyushkin authored
1 vmid limitation only exists for HOSTVM which is a custom use case anyway. Signed-off-by:
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Eric Yang authored
[Why] Renoir is gfx9, same as dcn10, not dcn20. Signed-off-by:
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Dmytro Laktyushkin authored
Renoir can use vm contexes as long as HOSTVM is off so this should be initialized. Signed-off-by:
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Lewis Huang authored
[Why] Watermarks not propagated to DCHUBP after it is powered on [How] Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Bhawanpreet Lakha authored
Incorrect page table address and programming sys aperture for stutter gather, so fix it. Signed-off-by:
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Dmytro Laktyushkin authored
Enabling hostvm when ROIMMU is not active seems to break GPUVM. This fixes the issue by not enabling hostvm if ROIMMU is not activated. Signed-off-by:
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Lewis Huang authored
[why] driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box [How] Move the patch function before calculate wm. Signed-off-by:
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Bhawanpreet Lakha authored
it allows us to do urgent latency programming Signed-off-by:
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Bhawanpreet Lakha authored
[Why] DCN20 and DCN21 have different phy programming sequences. [How] Create a separate dcn21_link_encoder for Renoir Signed-off-by:
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Bhawanpreet Lakha authored
This change adds renoir hw_seq, needed to do renoir specific hw programing Signed-off-by:
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Bhawanpreet Lakha authored
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Bhawanpreet Lakha authored
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