- 08 Oct, 2010 20 commits
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Jesse Barnes authored
Needed on Ibex Peak and Cougar Point or the panel won't always come on. Cc: stable@kernel.org Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
We don't use the CPU DP PLL with PCH attached eDP panels, so don't bother to enable it. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
We can skip most of the link training step if we use the VBT provided values. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
Cache the first 4 bytes of DPCD data in the eDP case. It's unlikely to change and can save us some trouble at link training time. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
We do this later (and more properly) when we enable FDI, so we don't need to do it here. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
Wait for vblank after enabling a pipe, make the error messages more informative, and wait for the pipe to turn off when we disable it. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
As with other PCH DP connections. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
CPU eDP needs a different reference clock than PCH eDP, which uses the standard PCH refclk of 120MHz. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
Enable SSC on PCH eDP if possible. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: added a posting read of PCH_DREF_CONTROL before the udelay] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
We need to use some of these values in eDP configurations, so be sure to fetch them and store them in the i915 private structure. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
The _DSM method on the integrated graphics device can tell us which connectors are muxable, so add support for making the call and parsing out the connector info. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: fix compiler warnings for using uninitialized 'result' and downgrade error message for non-switchable devices] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
Enable the panel before adjusting eDP link params, make sure the panel is idle after powering it on before proceeding with other activity, delay backlight enable to avoid visible flicker. Also avoid using VDD per hw team recommendation; it can conflict with the builtin panel power sequencing logic and lead to panel power sequencing failures. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
FDI training needs to done and idle for PCH eDP and before we turn the pipes on, and various eDP checks need to account for PCH attached eDP. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
Since we set the output type of PCH attached eDP panels to INTEL_OUTPUT_eDP this function would never return true when it should. It's been replaced by working functions. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
The display code needs to distinguish between CPU and PCH attached eDP panels, so add some helpers to handle that. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
With the old check we'd never set lane_count or bpp to different values on PCH attached eDP panels. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
If is_edp is true, is_pch_edp will always be true. So limit the calls to the latter function to places where the distinction actually matters. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
Most of the PCH eDP checks are redundant, so document the functions in preparation for removing most of the calls. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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- 07 Oct, 2010 2 commits
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Chris Wilson authored
Currently, if a batch buffer refers to an object with a pending flip, then we sleep until that pending flip is completed (unpinned and signalled). This is so that a flip can be queued and the user can continue rendering to the backbuffer oblivious to whether the buffer is still pinned as the scan out. (The kernel arbitrating at the last moment to stall the batch and wait until the buffer is unpinned and replaced as the front buffer.) As we only have a queue depth of 1, we can simply wait for the current pending flip to complete and continue rendering. We can achieve this with a single WAIT_FOR_EVENT command inserted into the ring buffer prior to executing the batch, *without* stalling the client. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Keith Packard authored
A physically mapped hardware status page is allocated at driver load time but was never freed. Call the existing code to free this page at driver unload time on hardware which uses this kind. Signed-off-by: Keith Packard <keithp@keithp.com> [ickle: call before tearing down registers on KMS-only path, as pointed out by Dave Airlie] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
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- 06 Oct, 2010 18 commits
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Dave Airlie authored
* 'drm-radeon-next' of ../drm-radeon-next: drm/radeon/kms: add drm blit support for evergreen drm/radeon: Modify radeon_pm_in_vbl to use radeon_get_crtc_scanoutpos() drm/radeon: Add function for display scanout position query. drm/radeon/kms: rework spread spectrum handling drm/radeon/kms: remove new pll algo drm/radeon/kms: remove some pll algo flags drm/radeon/kms: prefer high post dividers in legacy pll algo drm/radeon/kms: properly handle 40 bit MC addresses in the cursor code drm/radeon: add properties to configure the width of the underscan borders drm/radeon/kms/r6xx+: use new style fencing (v3) drm/radeon/kms: enable writeback (v2) drm/radeon/kms: clean up r6xx/r7xx blit init (v2)
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Dave Airlie authored
* drm-kdb-next: drm/nouveau/kms: Avoid a hang entering KDB with VT accel on. radeon, kdb, kms: Save and restore the LUT on atomic KMS enter/exit drm, kdb, kms: Add an enter argument to mode_set_base_atomic() API drm/nouveau/kms: Implement KDB debug hooks for nouveau KMS. drm/radeon/kms: Implement KDB debug hooks for radeon KMS.
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Dave Airlie authored
[airlied - add fix for vmwgfx build] * 'nouveau/for-airlied' of ../drm-nouveau-next: (93 commits) drm/ttm: restructure to allow driver to plug in alternate memory manager drm/ttm: introduce utility function to free an allocated memory node drm/nouveau: fix thinkos in mem timing table recordlen check drm/nouveau: parse voltage from perf 0x40 entires drm/nouveau: don't use the default pll limits in table v2.1 on nv50+ cards drm/nv50: Fix large 3D performance regression caused by the interchannel sync patches. drm/nouveau: Synchronize buffer object moves in hardware. drm/nouveau: Use semaphores to handle inter-channel sync in hardware. drm/nouveau: Provide a means to have arbitrary work run on fence completion. drm/nouveau: Minor refactoring/cleanup of the fence code. drm/nouveau: Add a module option to force card POST. drm/nv50: prevent (IB_PUT == IB_GET) for occurring unless idle drm/nv0x-nv4x: Leave the 0x40 bit untouched when changing CRE_LCD. drm/nv30-nv40: Fix postdivider mask when writing engine/memory PLLs. drm/nouveau: Fix perf table parsing on BMP v5.25. drm/nouveau: fix required mode bandwidth calculation for DP drm/nouveau: fix typo in c2aa91afea5f7e7ae4530fabd37414a79c03328c drm/nva3: split pm backend out from nv50 drm/nouveau: run perflvl and M table scripts on mem clock change drm/nouveau: pass perflvl struct to clock_pre() ...
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Chris Ball authored
Francisco Jerez advises that pre-nv20 cards would hang if we entered kdb with accel on and IRQs disabled, so we now disable accel before entering kdb and re-enable it on the way back out. Reported-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Jason Wessel authored
When changing VTs non-atomically the kernel works in conjunction with the Xserver in user space and receives the LUT information from the Xserver via a system call. When changing modes atomically for kdb, this information must be saved and restored without disturbing user space as if nothing ever happened. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> CC: Jesse Barnes <jbarnes@virtuousgeek.org> CC: David Airlie <airlied@linux.ie> CC: dri-devel@lists.freedesktop.org Signed-off-by: Dave Airlie <airlied@redhat.com>
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Jason Wessel authored
Some devices such as the radeon chips receive information from user space which needs to be saved when executing an atomic mode set operation, else the user space would have to be queried again for the information. This patch extends the mode_set_base_atomic() call to pass an argument to indicate if this is an entry or an exit from an atomic kernel mode set change. Individual drm drivers can properly save and restore state accordingly. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> CC: Jesse Barnes <jbarnes@virtuousgeek.org> CC: David Airlie <airlied@linux.ie> CC: dri-devel@lists.freedesktop.org Signed-off-by: Dave Airlie <airlied@redhat.com>
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Chris Ball authored
Tested on nv50 and nv04 HW. Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Jason Wessel <jason.wessel@windriver.com> CC: Jesse Barnes <jbarnes@virtuousgeek.org> CC: dri-devel@lists.freedesktop.org Signed-off-by: Dave Airlie <airlied@redhat.com>
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Chris Ball authored
Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Jason Wessel <jason.wessel@windriver.com> CC: Jesse Barnes <jbarnes@virtuousgeek.org> CC: dri-devel@lists.freedesktop.org Signed-off-by: Dave Airlie <airlied@redhat.com>
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Dave Airlie authored
* drm-vmware-next: drm/vmwgfx: Bump minor and driver date drm/vmwgfx: Save at least one screen layout drm/vmwgfx: Add modinfo version drm/vmwgfx: Add a parameter to get the max fb size drm/vmwgfx: Don't flush fb if we're in the suspended state. drm/vmwgfx: Prune modes based on available VRAM size drm/vmwgfx: Take the ttm lock around the dirty ioctl drm: vmwgfx: Add a struct drm_file parameter to the dirty framebuffer callback drm/vmwgfx: Add new-style PM hooks to improve hibernation behavior drm/vmwgfx: Fix ACPI S3 & S4 functionality. drm/vmwgfx: Really support other depths than 32
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Alex Deucher authored
This patch implements blit support for bo moves using the 3D engine. It uses the same method as r6xx/r7xx: - store the base state in an IB - emit variable state and vertex buffers to do the blit This allows the hw to move bos using the 3D engine and allows full use of vram beyond the pci aperture size. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Mario Kleiner authored
radeon_pm_in_vbl() didn't report in vblank status accurately. Make it a wrapper around radeon_get_crtc_scanoutpos() which corrects for biases, so it reports accurately. radeon_pm_in_vbl() will only report in_vbl if all active crtc's are currently inside vblank. agd5f: use rdev->num_crtc rather than hardcoding the crtc count Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Mario Kleiner authored
radeon_get_crtc_scanoutpos() returns the current horizontal and vertical scanout position of a crtc. It also reports if the display scanout is currently inside the vblank area. hpos reports current horizontal pixel scanout position. vpos reports the current scanned out line as a value >= 0 in active scanout. If the scanout is inside vblank area, it reports a negative value, the number of scanlines until end of vblank aka start of active scanout, e.g., -3 == "At most 3 scanlines until end of vblank". This code is derived from radeon_pm_in_vbl(), tested on R500 and R600. Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
This patch reworks spread spectrum handling to enable it properly on lvds and DP/eDP links. It also fixes several bugs in the old spread spectrum code. - Use the ss recommended reference divider if available when calculating the pll - Use the proper ss command tables on pre-DCE3 asics - Avoid reading past the end of the ss info tables - Enable ss on evergreen asics (lvds, dp, tmds) - Enable ss on DP/eDP links Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
The recent changes to the old algo (prefer high post div) coupled with the range and precision limitations of using fixed point with the new algo make the new algo less useful. So drop the new algo. This should work as well or better than the old new/old combinations and simplifies the code a lot. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=30218 among others. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
These shouldn't be needed with the post div changes in the last patch. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
the hw prefers higher post dividers Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Marius Gröger authored
This allows for a more exact fitting on the physical display. The new properties default to zero which corresponds to the previous underscan border width[height] formula: (display_width[display_width] >> 5) + 16. Example to set a horizontal border width of 30 and a vertikal border height of 22: xrandr --output HDMI-0 --set underscan on --set "underscan hborder" 30 --set "underscan vborder" 22 Signed-off-by: Marius Gröger <marius.groeger@googlemail.com> Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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