- 26 Oct, 2017 15 commits
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Chris Wilson authored
Recently W=1 on gcc-7.2 (-Wunused-const-variable) caught a regression that had been lurking for 6 months, so lets try enabling the full set of warnings for CI builds. This means more patches will be rejected early that contain trivial and sometimes not so trivial bugs. However, our code does not yet compile cleanly with W=1, so we have to apply a filter to the set of warnings until we can eliminate the mistakes. It also means that developers will have to be running the full gamut of gcc to ensure that as warnings come and go with gcc updates, we have the CI build prepared. v2: Use fine-grained -Wno overrides. Inside the makefile, we can specify CFLAGS on a per-object level, which allows us to limit the scope of any particular warning override. v3: Place per-file overrides after the main enabling block. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Tomi Sarvela <tomi.p.sarvela@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by:
Tomi Sarvela <tomi.p.sarvela@intel.com> Reviewed-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171024181547.27889-1-chris@chris-wilson.co.ukAcked-by:
Jani Nikula <jani.nikula@intel.com>
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Chris Wilson authored
Knowing the RING_MODE flags is useful for checking the state of the engine, such as whether the CS is idle after trying to stop the engines before reset. Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Michal Wajdeczko authored
Waiting for DMA status register can be done with dedicated function. Lets use it as additional bonus will be smaller driver footprint. Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by:
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Michał Winiarski authored
Pretty similar to what we have on execlists. We're reusing most of the GEM code, however, due to GuC quirks we need a couple of extra bits. Preemption is implemented as GuC action, and actions can be pretty slow. Because of that, we're using a mutex to serialize them. Since we're requesting preemption from the tasklet, the task of creating a workitem and wrapping it in GuC action is delegated to a worker. To distinguish that preemption has finished, we're using additional piece of HWSP, and since we're not getting context switch interrupts, we're also adding a user interrupt. The fact that our special preempt context has completed unfortunately doesn't mean that we're ready to submit new work. We also need to wait for GuC to finish its own processing. v2: Don't compile out the wait for GuC, handle workqueue flush on reset, no need for ordered workqueue, put on a reviewer hat when looking at my own patches (Chris) Move struct work around in intel_guc, move user interruput outside of conditional (Michał) Keep ring around rather than chase though intel_context v3: Extract WA for flushing ggtt writes to a helper (Chris) Keep work_struct in intel_guc rather than engine (Michał) Use ordered workqueue for inject_preempt worker to avoid GuC quirks. v4: Drop now unused INTEL_GUC_PREEMPT_OPTION_IMMEDIATE (Daniele) Drop stray newlines, use container_of for intel_guc in worker, check for presence of workqueue when flushing it, rather than enable_guc_submission modparam, reorder preempt postprocessing (Chris) v5: Make wq NULL after destroying it v6: Swap struct guc_preempt_work members (Michał) Signed-off-by:
Michał Winiarski <michal.winiarski@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jeff McGee <jeff.mcgee@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
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Michał Winiarski authored
We would also like to make use of execlist_cancel_port_requests and unwind_incomplete_requests in GuC preemption backend. Let's rename the functions to use the correct prefixes, so that we can simply add the declarations in the following patch. Similar thing for applies for can_preempt, except we're introducing HAS_LOGICAL_RING_PREEMPTION macro instad, converting other users that were previously touching device info directly. v2: s/intel_engine/execlists and pass execlists to unwind (Chris) v3: use locked version for exporting, drop const qual (Chris) Signed-off-by:
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Michał Winiarski authored
We also want to support preemption with GuC submission backend. In order to do that, we need to remember the priority, like we do on execlists path. v2: Remove completed prio == INT_MAX optimization Signed-off-by:
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Michał Winiarski authored
We shouldn't inspect ELSP context status (or any other bits depending on specific submission backend) when using GuC submission. Let's use another piece of HWSP for preempt context, to write its bit of information, meaning that preemption has finished, and hardware is now idle. Signed-off-by:
Jeff McGee <jeff.mcgee@intel.com> Signed-off-by:
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Michał Winiarski authored
Let's separate the "emit" part from touching any internal structures, this way we can have a generic "emit coherent GGTT write" function. We would like to reuse this functionality for emitting HWSP write, to confirm that preempt-to-idle has finished. v2: Reorder args to match emit_pipe_control, s/render/rcs (Chris) Signed-off-by:
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Michał Winiarski authored
We're using a special preempt context for HW to preempt into. We don't want to emit any requests there, but we still need to wrap this context into a valid GuC work item. Let's cleanup the functions operating on GuC work items. We can extract guc_request_add - responsible for adding GuC work item and ringing the doorbell, and guc_wq_item_append - used by the function above, not tied to the concept of gem request. Signed-off-by:
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Dave Gordon authored
This second client is created with priority KMD_HIGH, and marked as preemptive. This will allow us to request preemption using GuC actions. v2: Extract clients creation into a helper, debugfs fixups. (Michał) Recreate doorbell on init. (Daniele) Move clients into an array. v3: And move clients back from an array, to get rid of the enum (Michał) v4: Use is_high_priority, move DRM_ERROR into __create_doorbell, move GEM_BUG_ON inside guc_clients_create (Michał) v5: Split the BUG_ON (Michał) v6: Cleanup after error during doorbell reinit (Michał) Signed-off-by:
Dave Gordon <david.s.gordon@intel.com> Signed-off-by:
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Michał Winiarski authored
We're using GuC action to request preemption. However, after requesting preemption we need to wait for GuC to finish its own post-processing before we start submitting our requests. Firmware is using shared context to report its status. Let's update GuC firmware interface with those new definitions. v2: Drop unused INTEL_GUC_PREEMPT_OPTION_IMMEDIATE Signed-off-by:
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Michał Winiarski authored
We were using first page of kernel context render state for sharing data with GuC. While it's justified by the fact that those pages are not used (note, GuC still enforces this layout and refuses to work if we remove the extra page in front), it's also confusing (why are we using this particular page?). Let's allocate a separate object instead. v2: Drop kernel_context from GuC suspend/resume action handlers (Michel) Suggested-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:
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Michał Winiarski authored
Since it's a two-step process, we can have a cleaner error handling in the caller if we do the allocations in a helper. Signed-off-by:
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Michał Winiarski authored
Apparently, this value is reserved and may be interpreted as changing doorbell ownership. Even though we're not observing any side effects now, let's skip over it to be consistent with the spec. v2: Apply checkpatch (Sagar) Suggested-by:
Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by:
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Rodrigo Vivi authored
CNL adds an extra register for slice/subslice information. Although no SKU is planed with an extra slice let's already handle this extra piece of information so we don't have the risk in future of getting a part that might have chosen this part of the die instead of other slices or anything like that. Also if subslice is disabled the information of eu ack for that is garbage, so let's skip checks for eu if subslice is disabled as we skip the subslice if slice is disabled. The rest is pretty much like gen9. v2: Remove IS_CANNONLAKE from gen9 status function. v3: Consider s_max = 6 and ss_max=4 to run over all possible slices and subslices possible by spec. Although no real hardware will have that many slices/subslices. To match with sseu info init. v4: Fix offset calculation for slices 4 and 5. Removed Oscar's rv-b since this change also needs review. v5: Let's consider only valid bits for SLICE*_PGCTL_ACK. This looks like wrong in Spec, but seems to be enough for now. Whenever Spec gets updated and fixed we come back and properly update the masks. Also add a FIXME, so we can revisit this later when we find some strange info on debugfs or when we noitce spec got updated. Cc: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171026001546.28203-1-rodrigo.vivi@intel.com
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- 25 Oct, 2017 20 commits
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Michał Winiarski authored
Now that we're handling request resubmission the same way as regular submission (from the tasklet), we can move GuC initialization earlier, before restarting the engines. This way, we're no longer being in the state of flux during engine restart - we're already in user requested submission mode. Signed-off-by:
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Chris Wilson authored
The execlists emulation on top of the GuC (used for scheduling and preemption) depends on the MI_USER_INTERRUPT for its notifications and tasklet action. As we always employ the irq, there is no advantage in ever disabling it while we are using the GuC, so allow us to arm the breadcrumb irq when enabling GuC submission and disarm upon disabling. The impact should be lessened by the delayed irq disabling we do (we only disable after receiving an interrupt for which no one was wanting), but allowing guc to explicitly manage the irq in relation to itself is simpler and prevents an issue with losing an interrupt for preemption as it is not coupled to an active request. Internally, we add a reference counter (breadcrumbs.irq_enabled) as a simple mechanism to allow GuC to keep the breadcrumb irq enabled. To improve upon always enabling the irq while guc is selected, we need to hook into the parking facility of intel_engines so that we only enable the breadcrumbs while the GT is active (one step better would be to individually park/unpark each engine). In effect, this means that we keep the breadcrumb irq always enabled for the entire duration the guc is busy, whereas before we would try to switch it off whenever we idled for more than interrupt with no associated waiters. The difference *should* be negligible in practice! v2: Stop abusing fence signaling (and its auxiliary data structures) to enable the breadcrumbs irqs. Signed-off-by:
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Chris Wilson authored
In the next patch, we will want to install a callback when the engines (GT as a whole) become idle and similarly when they first become busy. To enable that callback, first rename intel_engines_mark_idle() to intel_engines_park() and provide the companion intel_engines_unpark(). Signed-off-by:
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Rodrigo Vivi authored
This is heavily based on a initial patch provided by Ville plus all changes provided later by Ander. As Geminilake, Cannonlake also supports 2 pixels per clock. Different from Geminilake we are not implementing the 99% Wa. But we can revisit that decision later if we find out any limitation on later CNL SKUs. v2: Rebase on top of commit 'd305e061 ("drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock")' v3: When fixing HDMI on CNL I noticed that I missed to convert back the doubled pixel rate to cdclk. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171003223142.26264-1-rodrigo.vivi@intel.com
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Joonas Lahtinen authored
When running under virtualization (vGPU active), we must disable the lazy PPGTT page table initialization optimization introduced by commit 14826673 ("drm/i915: Only initialize partially filled pagetables"). We must do this because GVT-g makes unduly assumptions about guest behaviour, which this optimization breaks. This results in following looking errors in the host: ERROR gvt: guest page write error -22, gfn 0x7ada8, pa 0x7ada89a8, var 0x6, len 1 The real fix is to not to depend on i915 driver behaviour, but instead either rely on only the contracts that i915 has with the hardware, or add some paravirtualization. While the real fix is en route, it won't be finished in time for 4.15, so the best option is to disable the optimization for now when vGPU is active to avoid breaking 4.15 guests in existing VM environments. Fixes: 14826673 ("drm/i915: Only initialize partially filled pagetables") Suggested-by:
Xiaolin Zhang <xiaolin.zhang@intel.com> Signed-off-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171023153209.10527-1-joonas.lahtinen@linux.intel.com
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Chris Wilson authored
This reverts commit 6d0dbd30. timer_setup_on_stack() does not yet exist: In file included from drivers/gpu/drm/i915/i915_sw_fence.c:517:0: drivers/gpu/drm/i915/selftests/lib_sw_fence.c: In function ‘timed_fence_init’: drivers/gpu/drm/i915/selftests/lib_sw_fence.c:63:2: error: implicit declaration of function ‘timer_setup_on_stack’; did you mean ‘hrtimer_init_on_stack’? [-Werror=implicit-function-declaration] timer_setup_on_stack(&tf->timer, timed_fence_wake, 0); Signed-off-by:
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Kees Cook authored
In preparation for unconditionally passing the struct timer_list pointer to all timer callbacks, switch to using the new timer_setup() and from_timer() to pass the timer pointer explicitly. Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: David Airlie <airlied@linux.ie> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by:
Kees Cook <keescook@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20171024151344.GA104417@beastReviewed-by:
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Chris Wilson authored
During evict, we wish to idle the GPU if we see that the GGTT is full. However, our test for idle in i915_gem_evict_something() and in i915_gem_switch_to_kernel_context() do not match leading to disappointment - we never believe that we are idle and keep trying to flush the GGTT ad infinitum. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103438Signed-off-by:
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Chris Wilson authored
Instead of trying to create a timer with zero delay (i.e. with expires set to the current jiffies and not the future, an already expired timer), execute that request immediately. v2: Refactor list_del_init+signal into its own little function. v3: Reorder testing so as not to immediately signal a delayed request. Signed-off-by:
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Chris Wilson authored
Insert a breakpoint, a chance to escape back to the scheduler and run something else for a bit, if we find that the GGTT is full and needs to be idled in order to make some room. In practice, this should only be an issue in stress tests as the wait itself will normally give the chance for the scheduler to intervene and make progress. References: https://bugs.freedesktop.org/show_bug.cgi?id=103438Signed-off-by:
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Ville Syrjälä authored
WARN if the cdclk state doesn't match what we expect after programming. And let's remove the WARN from bdw_set_cdclk() that's trying to achieve the same thing in a more limite fashion. Also take the opportunity to refactor the code to use a common function for dumping out a cdclk state. Cc: Mika Kahola <mika.kahola@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-11-ville.syrjala@linux.intel.comReviewed-by:
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Ville Syrjälä authored
chv_set_cdclk() sanity checks that the cdclk frequency is one of the legal values. Do the same in the VLV function. Cc: Mika Kahola <mika.kahola@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ville Syrjälä authored
On CNL we may need to bump up the system agent voltage not only due to CDCLK but also when driving DDI port with a sufficiently high clock. To that end start tracking the minimum acceptable voltage for each crtc. We do the tracking via crtcs because we don't have any kind of encoder state. Also there's no downside to doing it this way, and it matches how we track cdclk requirements on account of pixel rate. v2: Allow disabled crtcs to use the min voltage Add IS_CNL check to intel_ddi_compute_min_voltage() since we're using CNL specific values there s/intel_compute_min_voltage/cnl_compute_min_voltage/ since the function makes hw specific assumptions about the voltage values v3: Drop the test hack leftovers from skl_modeset_calc_cdclk() v4: s/voltage/voltage_level/ (Rodrigo) Replace DPLL DVFS FIXMEs with an explanation why we don't do anything there (Rodrigo) Cc: Mika Kahola <mika.kahola@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: -
Ville Syrjälä authored
Track the system agent voltage we request from pcode in the cdclk state on CNL. Annoyingly we can't actually read out the current value since there's no pcode command to do that, so we'll have to just assume that it worked. v2: s/voltage/voltage_level/ (Rodrigo) Cc: Mika Kahola <mika.kahola@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ville Syrjälä authored
Track the system agent voltage we request from pcode in the cdclk state on BXT/GLK. Annoyingly we can't actually read out the current value since there's no pcode command to do that, so we'll have to just assume that it worked. v2: s/voltage/voltage_level/ (Rodrigo) Cc: Mika Kahola <mika.kahola@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ville Syrjälä authored
Track the system agent voltage we request from pcode in the cdclk state on SKL/KBL/CFL. Annoyingly we can't actually read out the current value since there's no pcode command to do that, so we'll have to just assume that it worked. v2: s/voltage/voltage_level/ (Rodrigo) Cc: Mika Kahola <mika.kahola@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ville Syrjälä authored
Track the system agent voltage we request from pcode in the cdclk state on BDW. Annoyingly we can't actually read out the current value since there's no pcode command to do that, so we'll have to just assume that it worked. v2: Keep the WARN_ON (Rodrigo) v3: s/voltage/voltage_level/ (Rodrigo) Cc: Mika Kahola <mika.kahola@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ville Syrjälä authored
Store the punit DSPFREQUAR value into cdclk_state->voltage on VLV/CHV. Since we can actually read that out from the hardware this can give us a bit more cross checking between the hardware and software state. v2: Don't break waiting for cdclk change on VLV/CHV v3: Split out the cdclk sanity check in vlv_set_cdclk() (Rodrigo) v4: s/voltage/voltage_level/ (Rodrigo) Cc: Mika Kahola <mika.kahola@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ville Syrjälä authored
For CNL we'll need to start considering the port clocks when we select the voltage level for the system agent. To that end start tracking the voltage in the cdclk state (since that already has to adjust it). v2: s/voltage/voltage_level/ (Rodrigo) Cc: Mika Kahola <mika.kahola@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ville Syrjälä authored
Redo some switch statements in the cdclk code to use a common fall through for the default case. Makes everything look a bit more uniform Cc: Mika Kahola <mika.kahola@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-2-ville.syrjala@linux.intel.com
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- 24 Oct, 2017 5 commits
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Anusha Srivatsa authored
The latest version of DMC on CNL is 1.06. Update the version so as to load the latest firmware. Release Notes: Version: 1.06 1. DDI and AUX IO related fix. v2: Improve the prefixes in commit message. Add Release Notes directly. (Rodrigo) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
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Rodrigo Vivi authored
On CNL, individual wake rate limit was added to each engine. GT can only go to RC6 if both Render and Media engines are individually qualified. So we need to set their individual wake rate limit. +-----------------+---------------+--------------+--------------+ | | GT RC6 | Render C6 | Media C6 | +-----------------+---------------+--------------+--------------+ | Wake rate limit | 0xA09C[31:16] | 0xA09C[15:0] | 0xA0A0[15:0] | +-----------------+---------------+--------------+--------------+ v2: - Tune Render and Media wake rate values according to some extra info I got from HW engineers. Value can be tuned, but for now these are the recommended values. - Fix typos pointed by James. Cc: Nathan Ciobanu <nathan.d.ciobanu@intel.com> Cc: Wayne Boyer <wayne.boyer@intel.com> Cc: Joe Konno <joe.konno@linux.intel.com> Cc: David Weinehall <david.weinehall@linux.intel.com> Signed-off-by:James Ausmus <james.ausmus@intel.com> Reviewed-by:
David Weinehall <david.weinehall@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171023224612.27208-1-rodrigo.vivi@intel.com
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Rodrigo Vivi authored
As we faced in BXT, on CNL DDI_A_4_LANES is not set as expected when system is boot with multiple monitors connected. This result in wrong lane setup impacting the max data rate available and consequently blocking modeset on eDP, resulting in a blank screen. Most of CNL SKUs don't support DDI-E. The only SKU that supports DDI-E is the same that supports the full A/E split called DDI-F. Also when DDI-F is used DDI-E cannot be used because they share Interrupts. So DDI-E is almost useless. Anyways let's consider this is possible and rely on VBT for that. This patch was initialy start by Clint, but required many changes including full commit message. So Credits entirely to Clint for finding this. v2: Extract all messy conditions into a helper function as suggested by Ville. Along with simplification I removed the debug message on the working case since now all conditions are grouped. v3: Split the conditions even more as suggested by Ville. Get's cleaner and easier to add new cases in the future. Suggested-by:Clint Taylor <clinton.a.taylor@intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Lionel Landwerlin authored
The compat callback was missing and triggered failures in 32bits userspace when enabling/disable the perf stream. We don't require any particular processing here as these ioctls don't take any argument. Signed-off-by:
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Chris Wilson authored
Originally we set the priority to max upon inserting the request into the execlists queue (and removing it from the scheduler lists). We could then use the prio==INT_MAX as a shortcut within execlists_schedule() to detect the end of the dependency chain. Since commit 1f181225 ("drm/i915/execlists: Keep request->priority for its lifetime") this is no longer true as we use the request completion as an indicator the schedule dependency chain is complete instead. (This allows us to then reschedule requests even when its context is in flight.) However, this makes the GEM_BUG_ON() inside execlists_schedule() racy as we may change the rq->prio at the same time. As the assertion is useful, let's keep the assertion and remove the micro-optimisation. Fixes: 1f181225 ("drm/i915/execlists: Keep request->priority for its lifetime") Signed-off-by:
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