Skip to content

L
linux
Switch branch/tag
  1. 15 Mar, 2011 6 commits
    • Holger Brunck's avatar
      powerpc/8xx: remove obsolete mgsuvd board · 3cc5a0f0
      Holger Brunck authored 
      The MPC852 based mgsuvd board from Keymile was initially ported,
but later on not developed further. This patch removes the respective
files to decrease merging conflicts and unneeded maintenance.
Signed-off-by: default avatarHolger Brunck <holger.brunck@keymile.com>
Acked-by: Heiko Schocher<hs@denx.de>
Cc: Vitaly Bordug <vitb@kernel.crashing.org>
Cc: Marcelo Tosatti <marcelo@kvack.org>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      3cc5a0f0
    • Holger Brunck's avatar
      powerpc/82xx: rename and update mgcoge board support · c513e7c9
      Holger Brunck authored 
      The mgcoge board from keymile is now base for some other
similar boards. Therefore the board specific name mgcoge
was renamed to a generic name km82xx. Additionally some
enhancements were made:
	- rework partition table in dts file
	- add cpm2_pio_c gpio controller in dts file
	- update defconfig
	- add pin description for SCC1
	- add pin description and configuration for USB
Signed-off-by: default avatarHolger Brunck <holger.brunck@keymile.com>
Acked-by: default avatarHeiko Schocher <hs@denx.de>
CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: Heiko Schocher <hs@denx.de>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      c513e7c9
    • Holger Brunck's avatar
      powerpc/83xx: rename and update kmeter1 · 93e2b95c
      Holger Brunck authored 
      Beside the MPC 8360 based board kmeter1 other km83xx boards
from keymile will follow. Therefore the board specific naming
kmeter1 for functions and files were replaced with km83xx.
Additionally some updates were made:
    - update defconfig for 2.6.38
    - rework flash partitioning in dts file
    - add gpio controller for qe_pio_c in dts
Signed-off-by: default avatarHolger Brunck <holger.brunck@keymile.com>
Acked-by: default avatarHeiko Schocher <hs@denx.de>
CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: Heiko Schocher <hs@denx.de>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      93e2b95c
    • Liu Yu's avatar
      powerpc/85xx: Workaroudn e500 CPU erratum A005 · ac6f1203
      Liu Yu authored 
      This erratum can occur if a single-precision floating-point,
double-precision floating-point or vector floating-point instruction on a
mispredicted branch path signals one of the floating-point data interrupts
which are enabled by the SPEFSCR (FINVE, FDBZE, FUNFE or FOVFE bits).  This
interrupt must be recorded in a one-cycle window when the misprediction is
resolved.  If this extremely rare event should occur, the result could be:

The SPE Data Exception from the mispredicted path may be reported
erroneously if a single-precision floating-point, double-precision
floating-point or vector floating-point instruction is the second
instruction on the correct branch path.

According to errata description, some efp instructions which are not
supposed to trigger SPE exceptions can trigger the exceptions in this case.
However, as we haven't emulated these instructions here, a signal will
send to userspace, and userspace application would exit.

This patch re-issue the efp instruction that we haven't emulated,
so that hardware can properly execute it again if this case happen.
Signed-off-by: default avatarLiu Yu <yu.liu@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      ac6f1203
    • Prabhakar Kushwaha's avatar
      powerpc/fsl_pci: Add support for FSL PCIe controllers v2.x · f4154e16
      Prabhakar Kushwaha authored 
      FSL PCIe controller v2.1:
     - New MSI inbound window
     - Same Inbound windows address as PCIe controller v1.x

Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window

FSL PCIe controller v2.2 and v2.3:
     - Different addresses for PCIe inbound window 3,2,1
     - Exposed PCIe inbound window 0
     - New PCIe interrupt status register

Added new config and interrupt Status register to struct ccsr_pci & updated
pit_t array size to reflect the 4 inbound windows.

Device tree is used to maintain backward compatibility i.e. update inbound
window 1 index depending upon "compatible" field witin PCIE node.
Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      f4154e16
    • Kumar Gala's avatar
      powerpc/85xx: Fix writing to spin table 'cpu-release-addr' on ppc64e · decbb280
      Kumar Gala authored 
      If the spin table is located in the linear mapping (which can happen if
we have 4G or more of memory) we need to access the spin table via a
cacheable coherent mapping like we do on ppc32 (and do explicit cache
flush).

See the following commit for the ppc32 version of this issue:

commit d1d47ec6
Author: Peter Tyser <ptyser@xes-inc.com>
Date:   Fri Dec 18 16:50:37 2009 -0600

    powerpc/85xx: Fix SMP when "cpu-release-addr" is in lowmem
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      decbb280
  3. 11 Mar, 2011 1 commit
  5. 10 Mar, 2011 28 commits
  7. 04 Mar, 2011 4 commits
  9. 02 Mar, 2011 1 commit
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7