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- 27 Oct, 2010 5 commits
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Chris Wilson authored
Signed-off-by:Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
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Chris Wilson authored
The render ring is not alone any more! And the other rings are just as troublesome... Signed-off-by: -
Chris Wilson authored
Preparing the ringbuffer for adding new commands can fail (a timeout whilst waiting for the GPU to catch up and free some space). So check for any potential error before overwriting HEAD with new commands, and propagate that error back to the user where possible. Signed-off-by: -
Chris Wilson authored
The ringbuffer keeps a pointer to the parent device, so we can use that instead of passing around the pointer on the stack. Signed-off-by:
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- 24 Oct, 2010 1 commit
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Chris Wilson authored
... to prevent flush processing of an idle (or even absent) ring. This fixes a regression during suspend from 87acb0a5. Reported-and-tested-by:
Alexey Fisher <bug-track@fisher-privat.net> Tested-by:
Peter Clifton <pcjc2@cam.ac.uk> Signed-off-by:
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- 22 Oct, 2010 1 commit
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Chris Wilson authored
This should fix the error along the reset path were we tried to clear the tail register by setting it to 0, but were in fact setting it to the current value and complaining when it did not reset to 0. Signed-off-by:
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- 21 Oct, 2010 2 commits
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Chris Wilson authored
Based on an original patch by Zhenyu Wang, this initializes the BLT ring for SandyBridge and enables support for user execbuffers. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: -
Chris Wilson authored
... before someone tries to use it. The code both calls intel_ring_begin/advance() and open-codes the bookkeeping performed by those two functions. Signed-off-by:
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- 28 Sep, 2010 1 commit
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Chris Wilson authored
With multiple rings generating requests independently, the outstanding requests must also be track independently. Reported-by:
Wang Jinjin <jinjin.wang@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30380Signed-off-by:
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- 25 Sep, 2010 2 commits
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Daniel Vetter authored
It's the same code, essentially, so kill all copies safe one unified version. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Daniel Vetter authored
All functions are extremely similar, so fold them into one generic implementation. This function isn't used anyway, because there's not yet a bsd ring error state dumper. Signed-off-by:
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- 24 Sep, 2010 2 commits
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Chris Wilson authored
Avoid cause latencies in other clients by not taking the global struct mutex and moving the per-client request manipulation a local per-client mutex. For example, this allows a compositor to schedule a page-flip (through X) whilst an OpenGL application is monopolising the GPU. Signed-off-by: -
Chris Wilson authored
As we presume space is signed when computing and looking for wrap along, make it so. Reported-by:
Owain G. Ainsworth <zerooa@googlemail.com> Signed-off-by:
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- 22 Sep, 2010 1 commit
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Chris Wilson authored
We are not currently using it as intended, so remove the complication. Signed-off-by:
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- 21 Sep, 2010 11 commits
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Chris Wilson authored
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Daniel Vetter authored
Always PAGE_SIZE and only complicates the code. Signed-off-by:
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Daniel Vetter authored
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Daniel Vetter authored
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Daniel Vetter authored
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Daniel Vetter authored
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Daniel Vetter authored
Documentation explicitly mentions that the ring registers are designed to have the same offsets relative to a base registers. Use this to fight the code beaurocratic in intel_ringbuffer.c. No code changes in this patch, just the new definitions. Signed-off-by:
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Chris Wilson authored
As noted by Zhenyu, we can now simply replace the existing advance hook by calling the new set_tail function pointer directly. Signed-off-by: -
Xiang, Haihao authored
This is prepared for video codec ring buffer on Sandybridge. It is needed to read/write more than one register to move the tail pointer of the video codec ring on Sandybridge. Signed-off-by:
Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by:
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Xiang, Haihao authored
Introduce intel_init_render_ring_buffer(), intel_init_bsd_ring_buffer for ring initialization. Signed-off-by:
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Chris Wilson authored
When flushing the GPU domains,we emit a flush on *both* rings, even though they share a unified cache. Only emit the flush on the currently active ring. Signed-off-by:
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- 14 Sep, 2010 1 commit
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Chris Wilson authored
This can always be re-added should somebody find a use... Signed-off-by:
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- 08 Sep, 2010 1 commit
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Daniel Vetter authored
Previously I thought that one interrupt per batchbuffer should be enough. Now tedious benchmarking showed this to be wrong. Therefore track whether any commands have been isssued with a future seqno (like pipelined fencing changes or flushes). If this is the case emit a request before issueing the batchbuffer. Signed-off-by:
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- 09 Aug, 2010 2 commits
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Chris Wilson authored
This will be used by the eviction logic to maintain fairness between the rings. Signed-off-by:
Eric Anholt <eric@anholt.net>
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Chris Wilson authored
As the function has been reduced to a store plus increment, the body is now smaller than the call so inline it. Signed-off-by:
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- 26 May, 2010 1 commit
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Zou Nan hai authored
Introduces a more complete intel_ring_buffer structure with callbacks for setup and management of a particular ringbuffer, and converts the render ring buffer consumers to use it. Signed-off-by:
Zou Nan hai <nanhai.zou@intel.com> Signed-off-by:
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