- 14 Sep, 2016 1 commit
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git://linuxtv.org/snawrocki/samsungStephen Boyd authored
Pull samsung clk driver updates from Sylwester Nawrocki: In addition to a few clean up and code consolidation patches this includes: - addition of sound subsystem related clocks for Exynos5410 SoC (EPLL, PDMA) and support for "samsung,exynos5410-audss-clock" compatible in the clk-exynos-audss driver, - addition of DRAM controller related clocks for exynos5420, - MAINTAINERS update adding Chanwoo Choi as the Samsung SoC clock drivers co-maintainer. * tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: Add support for EPLL on exynos5410 clk: samsung: clk-exynos-audss: Whitespace and debug trace cleanup clk: samsung: clk-exynos-audss: Add exynos5410 compatible clk: samsung: clk-exynos-audss: controller variant handling rework clk: samsung: Use common registration function for pll2550x clk: samsung: exynos5410: Expose the peripheral DMA gate clocks clk: samsung: exynos5420: Add clocks for CMU_CDREX domain clk: samsung: exynos5410: Use samsung_cmu_register_one() to simplify code clk: samsung: exynos5260: Move struct samsung_cmu_info to init section MAINTAINERS: Add myself as Samsung SoC clock drivers co-maintainer clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller)
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- 09 Sep, 2016 13 commits
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Tomeu Vizoso authored
Right now we are passing a pointer to a pointer to the structure that will be used to fetch the clk hw, which gets casted later to a pointer to the structure, thus getting garbage in the hw structs. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Fixes: a8b6e85d ("clk: rk808: Migrate to clk_hw based OF and registration APIs") Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Sylwester Nawrocki authored
This patch adds code instantiating the EPLL, which is used as the audio subsystem's root clock. The requirement to specify the external root clock in clocks property is documented. Having the consumer 'clocks' property ensures proper initialization order by explicitly specifying dependencies in DT. It prevents situations when the SoC's clock controller driver has initialized, the external oscillator clock is not yet registered and setting clock frequencies through assigned-clock-rates property doesn't work properly due to unknown external oscillator frequency. Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by:
Chanwoo Choi <cw00.choi@samsung.com>
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Sylwester Nawrocki authored
There is no need to log probe() completion in normal conditions so the "setup completed" log is removed. Signed-off-by: -
Sylwester Nawrocki authored
Exynos5410 Audio Subsystem Clock Controller, comparing to the already supported IP block revisions, has additionally an I2S_MST divider so a new compatible string is added. It is not clear from the Exynos5410 User's Manual released on 2012.03.09 where in the clock tree the I2S_MST clock divider can be found exactly so this clock is left unimplemented for now. Signed-off-by: -
Sylwester Nawrocki authored
Then variant handling is reworked to make the code simpler when more variants are added. Signed-off-by: -
Sylwester Nawrocki authored
There is no such significant differences in pll2550x PLL type to justify a separate registration function. This patch adapts exynos5440 driver to use the common function and removes samsung_clk_register_pll2550x(). Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by:
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Sylwester Nawrocki authored
These clocks are needed in order to use the PL330 peripheral DMA controllers. Signed-off-by: -
Chanwoo Choi authored
This patch adds the mux/divider clocks for CMU_CDREX (DRAM Express Controller) which generates the clocks for DRAM and NoC (Network on Chip) bus. There is differnet source of MUX_MX_MSPLL_CCORE between exynos5420 and exynos5422, so each MUX_MX_MSPLL_CCORE uses the different parent source group. Signed-off-by:
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Chanwoo Choi authored
This patch uses the samsung_cmu_register_one() to simplify code and move the pll/mux/div/gate data to initconst section. Signed-off-by:
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Chanwoo Choi authored
This patch moves the samsung_cmu_info struct instances to initconst section, this decreases the kernel image size by 784 bytes, which makes zImage smaller by 480 bytes. The patch increases .init.rodata section size by 780 bytes but decreases .init.text section size by 1564 bytes. Size of the drivers/clk/samsung/clk-exynos5260.o object file is 29100 bytes without the patch and 28316 after applying the patch. The section size differences are as below: 15c15 < 3 .init.text 000006b8 00000000 00000000 00000034 2**2 --- > 3 .init.text 0000009c 00000000 00000000 00000034 2**2 25c25 < 8 .init.rodata 00003f6c 00000000 00000000 00002f20 2**2 --- > 8 .init.rodata 00004278 00000000 00000000 00002904 2**2 Signed-off-by:
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Chanwoo Choi authored
Add myself to the SAMSUNG SOC CLOCK DRIVERS entry, I'm going to review and test related patches as supporter. I can access all the datasheet of Exynos SoC series and can do tests on Exynos based boards. I have implemented the exynos4415/5433 clock drivers and co-authored the exynos3250 clock driver. While at it, add missing paths of the exynos clock driver files. Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by:
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Sylwester Nawrocki authored
The PDMA{0,1} and EPLL clock IDs are added separately in this patch so the patch can be merged to the arm-soc tree as dependency. Signed-off-by: -
Chanwoo Choi authored
This patch adds missing clock IDs for CMU_CDREX (DRAM Express Controller) which generates clocks for DRAM and NoC (Network on Chip) busses. Signed-off-by:
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- 08 Sep, 2016 2 commits
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Stephen Boyd authored
* clk-fixes: clk: sunxi-ng: Fix wrong reset register offsets clk: sunxi-ng: nk: Make ccu_nk_find_best static clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock clk: sunxi: Fix return value check in sun8i_a23_mbus_setup() clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()
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Stephen Boyd authored
Merge tag 'sunxi-clk-fixes-for-4.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes Clock Fixes for the Allwinner SoCs, 4.8 Edition The usual bunch of fixes to the our clock drivers, mostly targetted to the brand new sunxi-ng drivers. * tag 'sunxi-clk-fixes-for-4.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi-ng: Fix wrong reset register offsets clk: sunxi-ng: nk: Make ccu_nk_find_best static clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock clk: sunxi: Fix return value check in sun8i_a23_mbus_setup() clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()
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- 07 Sep, 2016 6 commits
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Eric Anholt authored
If the firmware had set up a clock to source from PLLC, go along with it. But if we're looking for a new parent, we don't want to switch it to PLLC because the firmware will force PLLC (and thus the AXI bus clock) to different frequencies during over-temp/under-voltage, without notification to Linux. On my system, this moves the Linux-enabled HDMI state machine and DSI1 escape clock over to plld_per from pllc_per. EMMC still ends up on pllc_per, because the firmware had set it up to use that. Signed-off-by:
Eric Anholt <eric@anholt.net> Fixes: 41691b88 ("clk: bcm2835: Add support for programming the audio domain clocks") Acked-by:
Martin Sperl <kernel@martin.sperl.org> Signed-off-by:
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Eric Anholt authored
While the SDRAM is being driven by its dedicated PLL most of the time, there is a little loop running in the firmware that periodically turns on the CM SDRAM clock (using its pre-initialized parent) and switches SDRAM to using the CM clock to do PVT recalibration. This avoids system hangs if we choose SDRAM's parent for some other clock, then disable that clock. Signed-off-by:
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Eric Anholt authored
These divide off of PLLD_PER and are used for the ethernet and wifi PHYs source PLLs. Neither of them is currently represented by a phy device that would grab the clock for us. This keeps other drivers from killing the networking PHYs when they disable their own clocks and trigger PLLD_PER's refcount going to 0. Signed-off-by:
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Eric Anholt authored
The VPU clock is also the clock for our AXI bus, so we really can't disable it. This might have happened during boot if, for example, uart1 (aux_uart clock) probed and was then disabled before the other consumers of the VPU clock had probed. Signed-off-by:
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Stephen Boyd authored
Merge tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: The biggest addition is probably the special clock-type for ddr clock control. While reading that clock is done the normal way from the registers, setting it always requires some sort of special handling to let the system survive this addition. As the commit message explains, there are currently 3 handling-types known. General SRAM-based code on rk3288 and before (which is waiting essentially for the PIE support that is currently being worked on), SCPI-based clk setting on the rk3368 through a coprocessor, which we might support once the support for legacy scpi-variants has matured and now on the rk3399 (and probably later) using a dcf controller that is controlled from the arm-trusted-firmware and gets accessed through firmware calls from the kernel. This is the variant we currently support, but the clock type is made to support the other variants in the future as well. Apart from that slightly bigger chunk, we have a mix of PLL rates, clock-ids and flags mainly for the rk3399. And interestingly an iomap fix for the legacy gate driver, where I hopefully could deter the submitter from actually using that in any new works. * tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: use the dclk_vop_frac clock ids on rk3399 clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers clk: rockchip: add 2016M to big cpu clk rate table on rk3399 clk: rockchip: add rk3399 ddr clock support clk: rockchip: add dclk_vop_frac ids for rk3399 vop clk: rockchip: add new clock-type for the ddrclk soc: rockchip: add header for ddr rate SIP interface clk: rockchip: add SCLK_DDRC id for rk3399 ddrc clk: rockchip: handle of_iomap failures in legacy clock driver clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical clk: rockchip: use general clock flag when registering pll clk: rockchip: delete the CLK_IGNORE_UNUSED from aclk_pcie on rk3399 clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI
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Geert Uytterhoeven authored
Add a section for Renesas clock drivers, as found on Renesas ARM SoCs, and list myself as the maintainer. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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- 04 Sep, 2016 6 commits
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Yakir Yang authored
Export the dclk_vop_frac out, so we can set the dclk_vop as the child of dclk_vop_frac, and then we can start to take use of the fractional dividers. Signed-off-by:
Yakir Yang <ykk@rock-chips.com> Signed-off-by:
Chris Zhong <zyw@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Douglas Anderson authored
Currently the fractional divider clock time can't handle the CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers, there is no clk_divider_bestdiv() function to try speeding up the parent to see if it helps things. Eventually someone could try to figure out how to make fractional dividers able to use CLK_SET_RATE_PARENT, but until they do let's not confuse the common clock framework (and anyone using it) by setting the flag. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Shunqian Zheng authored
We would prefer the 2016M as 2.0G than 1992M which seems odd, adding it to big cpu clk rate table then we can set 2016M in dts. Signed-off-by:
Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by:
Xing Zheng <zhengxing@rock-chips.com> Signed-off-by:
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Lin Huang authored
add ddrc clock setting, so we can do ddr frequency scaling on rk3399 platform in future. Signed-off-by:
Lin Huang <hl@rock-chips.com> Signed-off-by:
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Heiko Stuebner authored
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Yakir Yang authored
Export the dclk_vop_frac out, so we can set the dclk_vop as the child of dclk_vop_frac, and then we can start to take use of the fractional dividers. Signed-off-by:
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- 03 Sep, 2016 1 commit
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Michael Turquette authored
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- 02 Sep, 2016 8 commits
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Neil Armstrong authored
Add the PWM related clocks in order to be referenced as PWM source clocks. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1471870177-10609-1-git-send-email-narmstrong@baylibre.com
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Alexander Müller authored
This patch adds support for the meson8b clock gates. Most of them are disabled by Amlogic U-Boot, but need to be enabled for ethernet, USB and many other components. Signed-off-by:
Alexander Müller <serveralex@gmail.com> Signed-off-by:
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Alexander Müller authored
The macro used gxbb_ prefix for clock definitions. In order to share the macro between gxbb and meson8b, the prefix must be moved to gxbb.c. Signed-off-by:
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Alexander Müller authored
Only expose future CLKID constants if necessary. This patch removes CLK_NR_CLKS from the DT bindings but leaves all previously defined CLKIDs there to keep backward compatibility. Signed-off-by:
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Alexander Müller authored
Signed-off-by:
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Alexander Müller authored
Move the register definitions into a separate header file to reflect the gxbb implementation. Signed-off-by:
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Alexander Müller authored
Signed-off-by:
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Michael Turquette authored
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- 01 Sep, 2016 2 commits
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Lin Huang authored
Changing the rate of the DDR clock needs special care, as the DDR is of course in use and will react badly if the rate changes under it. Over time different approaches to handle that were used. Past SoCs like the rk3288 and before would store some code in SRAM while the rk3368 used a SCPI variant and let a coprocessor handle that. New rockchip platforms like the rk3399 have a dcf controller to do ddr frequency scaling, and support for this controller will be implemented in the arm-trusted-firmware. This new clock-type should over time handle all these methods for handling DDR rate changes, but right now it will concentrate on the SIP interface used to talk to ARM trusted firmware. The SIP interface counterpart was merged from pull-request #684 [0] into the upstream arm-trusted-firmware codebase. [0] https://github.com/ARM-software/arm-trusted-firmware/pull/684Signed-off-by:
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Heiko Stuebner authored
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- 31 Aug, 2016 1 commit
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Lin Huang authored
Add a header for the SIP interface defined to access the dcf controller handling ddr rate changes on rk3399 (and most likely later socs). This interface is shared between the clock driver as well as the devfreq driver. The SIP interface counterpart was merged from pull-request #684 [0] into the upstream arm-trusted-firmware codebase. [0] https://github.com/ARM-software/arm-trusted-firmware/pull/684Signed-off-by:
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