- 10 Mar, 2012 1 commit
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Alan Cox authored
Signed-off-by:
Alan Cox <alan@linux.intel.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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- 07 Mar, 2012 1 commit
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Rob Clark authored
If there are not multiple instances of a platform device, the id should apparently be set to -1. Which results in a odd looking bus-id like "platform:foodrm:-1". Probably we should just treat this case as id 0. Signed-off-by:
Rob Clark <rob@ti.com> Signed-off-by:
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- 05 Mar, 2012 1 commit
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Dave Airlie authored
Talking to Al Viro on irc, we can see no possible reason for doing this, the upper mmap code does it. The code has been there since first import into drm tree I can find. Al tracked down this as a requirement pre 2.3.51 hasn't been needed since. Acked-by:
Al Viro <viro@zeniv.linux.org.uk> Signed-off-by:
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- 29 Feb, 2012 15 commits
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Felix Kuehling authored
This fixes page-flip-related flickering observed on Iconia Tab W500. The update_pending status returned by radeon_page_flip is very accurate on Avivo-based ASICs when vpos is negative. Experiments were conducted on several ASIC generations ranging from RS690 to Cayman where the page flip was artificially timed to occur at a specific vpos. With negative vpos, overriding update_pending always lead to flickering. The same experiment on RV380 and RV410 showed that update_pending is not accurate with negative vpos. In most cases update_pending == 1 is returned although the flip would complete before the start of the next frame. Therefore I left the behaviour unchanged for pre-AVIVO ASICs for performance reasons, although this may result in flickering in rare cases. This change also makes the logic a little easier to understand. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by:
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Sascha Hauer authored
remove declared but unused functions from drmP.h, fix the comments where necessary. Also, remove drm_mem_info which is unused. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
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Alex Deucher authored
v2: fix typo. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König<christian.koenig@amd.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Jerome Glisse <jglisse@redhat.com> Signed-off-by:
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Alex Deucher authored
tidy up the radeon_asic struct. Signed-off-by:
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Alex Deucher authored
tidy up radeon_asic struct. Signed-off-by:
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Alex Deucher authored
tidy up the radeon_asic struct. Signed-off-by:
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Alex Deucher authored
tidy up the radeon_asic struct. Signed-off-by:
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Alex Deucher authored
Each ring type may need a different variant. Signed-off-by:
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Alex Deucher authored
Signed-off-by:
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Alex Deucher authored
tidy up the radeon_asic struct. Signed-off-by:
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Alex Deucher authored
tidy up the radeon_asic struct, handle multiple rings better. Signed-off-by:
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Christian König authored
Storing pointers to the IBs in a static var just leads to giving the same content back for all cards in the system. Signed-off-by:
Christian König <deathsimple@vodafone.de> Reviewed-by:
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Christian König authored
Not all rings use PM4, so the cs_parser also needs to be per ring. Signed-off-by:
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Christian König authored
So don't confuse devs by doing so. Signed-off-by:
Alex Deucher <alex.deucher@amd.com> Signed-off-by:
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Christian König authored
The function radeon_bo_list_validate can cause a bo to move, resulting in a different sync_obj and a dependency to wait for this move to finish. Signed-off-by:
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- 27 Feb, 2012 5 commits
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Alex Deucher authored
tidy up the radeon_asic struct. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Alex Deucher authored
tidy up the radeon_asic struct. Signed-off-by:
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Alex Deucher authored
tidy up the radeon_asic struct. Signed-off-by:
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Alex Deucher authored
Required for future functionality. Signed-off-by:
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Alex Deucher authored
Required for future functionality. Signed-off-by:
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- 23 Feb, 2012 2 commits
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Dave Airlie authored
Merge tag 'drm-intel-next-2012-02-16-merge-resolved' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next * tag 'drm-intel-next-2012-02-16-merge-resolved' of git://people.freedesktop.org/~danvet/drm-intel: (45 commits) Revert "drivers/gpu/drm/i915/intel_overlay.c needs seq_file.h" drm/i915/lvds: Always use the presence pin for LVDS on PCH drm/i915: Record the position of the request upon error drm/i915: Record the in-flight requests at the time of a hang drm/i915: Record the tail at each request and use it to estimate the head drm/i915: add missing SDVO bits for interlaced modes on ILK drm/i915: Fix race condition in accessing GMBUS drm/i915: add a "force-dvi" HDMI audio mode drm/i915: Don't lock panel registers when downclocking drm/i915: fix up locking inconsistency around gem_do_init drm/i915: enable forcewake voodoo also for gen6 drm/i915: fixup seqno allocation logic for lazy_request drm/i915: outstanding_lazy_request is a u32 drm/i915: check gtfifodbg after possibly failed writes drm/i915: catch gtfifo errors on forcewake_put drm/i915: use gtfifodbg drm/i915: set interlaced bits for TRANSCONF drm/i915: fixup overlay checks for interlaced modes drm/i915: allow interlaced mode output on the HDMI connector drm/i915: allow interlaced mode output on the SDVO connector ...
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Daniel Vetter authored
Manually resolve the conflict between the new enum drm property helpers in drm-next and the new "force-dvi" option that the "audio" output property gained in drm-intel-next. While resolving this conflict, switch the new drm_prop_enum_list to use the newly introduced enum defines instead of magic values. Conflicts: drivers/gpu/drm/i915/intel_modes.c Signed-Off-by:Daniel Vetter <daniel.vetter@ffwll.ch>
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- 16 Feb, 2012 4 commits
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Dave Airlie authored
For the simple KMS driver case we need some more info about what the preferred depth and if a shadow framebuffer is preferred. I've only added this for intel/radeon which support the dumb ioctls so far. If you need something really fancy you should be writing a real X.org driver. v2: drop cursor information, just return an error from the cursor ioctls and we can make userspace fallback to sw cursor in that case, cursor info was getting too messy, best to start smaller. Signed-off-by: -
Dave Airlie authored
The current enabling of bus mastering in the drm midlayer allows a large race condition under kexec. When a kexec'ed kernel re-enables bus mastering for the GPU, previously setup dma blocks may cause writes to random pieces of memory. On radeon the writeback mechanism can cause these sorts of issues. This patch doesn't fix the problem, but it moves the bus master enable under the individual drivers control so they can move enabling it until later in their load cycle and close the race. Fix for radeon kms driver will be in a follow-up patch. Signed-off-by: -
Danny Kukawka authored
This reverts commit e167976e, Since this was already fixed in commit 3bd3c932 some days before this commit cause seq_file.h to be included twice. Signed-off-by:
Danny Kukawka <danny.kukawka@bisect.de> Signed-off-by:
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Dan Carpenter authored
We store stuff in texdw[7] so this array needs to have 8 elements. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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- 15 Feb, 2012 4 commits
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Chris Wilson authored
With the introduction of the PCH, we gained an LVDS presence pin but we continued to use the existing logic that asserted that LVDS was only supported on certain mobile chipsets. However, there are desktop IronLake systems with LVDS attached which we fail to detect. So for PCH, trust the LVDS presence pin and quirk all the lying manufacturers. Tested-by:
Daniel Woff <wolff.daniel@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43171Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by:
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Chris Wilson authored
So that we can tally the request against the command sequence in the ringbuffer, or merely jump to the interesting locations. Signed-off-by:
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Chris Wilson authored
Being able to tally the list of outstanding requests with the sequence of commands in the ringbuffer is often useful evidence with respect to driver corruption. Note that since this is the umpteenth per-ring data structure to be added to the error state, I've coallesced the nearby loops (the ringbuffer and batchbuffer) into a single structure along with the list of requests. A later task would be to refactor the ring register state into the same structure. v2: Fix pretty printing of requests so that they are parsed correctly by intel_error_decode and use the 0x%08x format for seqno for consistency Signed-off-by:
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Chris Wilson authored
By recording the location of every request in the ringbuffer, we know that in order to retire the request the GPU must have finished reading it and so the GPU head is now beyond the tail of the request. We can therefore provide a conservative estimate of where the GPU is reading from in order to avoid having to read back the ring buffer registers when polling for space upon starting a new write into the ringbuffer. A secondary effect is that this allows us to convert intel_ring_buffer_wait() to use i915_wait_request() and so consolidate upon the single function to handle the complicated task of waiting upon the GPU. A necessary precaution is that we need to make that wait uninterruptible to match the existing conditions as all the callers of intel_ring_begin() have not been audited to handle ERESTARTSYS correctly. By using a conservative estimate for the head, and always processing all outstanding requests first, we prevent a race condition between using the estimate and direct reads of I915_RING_HEAD which could result in the value of the head going backwards, and the tail overflowing once again. We are also careful to mark any request that we skip over in order to free space in ring as consumed which provides a self-consistency check. Given sufficient abuse, such as a set of unthrottled GPU bound cairo-traces, avoiding the use of I915_RING_HEAD gives a 10-20% boost on Sandy Bridge (i5-2520m): firefox-paintball 18927ms -> 15646ms: 1.21x speedup firefox-fishtank 12563ms -> 11278ms: 1.11x speedup which is a mild consolation for the performance those traces achieved from exploiting the buggy autoreported head. v2: Add a few more comments and make request->tail a conservative estimate as suggested by Daniel Vetter. Signed-off-by:
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- 14 Feb, 2012 4 commits
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Paulo Zanoni authored
This was pointed by Jesse Barnes. The code now seems to follow the specification but I don't have an SDVO device to really test this. Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-intel-next-2012-02-07' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next * tag 'drm-intel-next-2012-02-07' of git://people.freedesktop.org/~danvet/drm-intel: (29 commits) drm/i915: Handle unmappable buffers during error state capture drm/i915: rewrite shmem_pread_slow to use copy_to_user drm/i915: rewrite shmem_pwrite_slow to use copy_from_user drm/i915: fall through pwrite_gtt_slow to the shmem slow path drm/i915: add debugfs file for swizzling information drm/i915: fix swizzle detection for gen3 drm/i915: Remove the upper limit on the bo size for mapping into the CPU domain drm/i915: add per-ring fault reg to error_state drm/i915: reject GTT domain in relocations drm/i915: remove the i915_batchbuffer_info debugfs file drm/i915: capture error_state also for stuck rings drm/i915: refactor debugfs create functions drm/i915: refactor debugfs open function drm/i915: don't trash the gtt when running out of fences drm/i915: Separate fence pin counting from normal bind pin counting drm/i915/ringbuffer: kill snb blt workaround drm/i915: collect more per ring error state drm/i915: refactor ring error state capture to use arrays drm/i915: switch ring->id to be a real id drm/i915: set AUD_CONFIG N_value_index for DisplayPort ...
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Yufeng Shen authored
GMBUS has several ports and each has it's own corresponding I2C adpater. When multiple I2C adapters call gmbus_xfer() at the same time there is a race condition in using the underlying GMBUS controller. Fixing this by adding a mutex lock when calling gmbus_xfer(). v2: Moved gmbus_mutex below intel_gmbus and added comments. Rebased to drm-intel-next-queued. Signed-off-by:
Yufeng Shen <miletus@chromium.org> [danvet: Shortened the gmbus_mutex comment a bit and add the patch revision comment to the commit message.] Signed-off-by:
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Wu Fengguang authored
When HDMI-DVI converter is used, it's not only necessary to turn off audio, but also to disable HDMI_MODE_SELECT and video infoframe. Since the DVI mode is mainly tied to audio functionality from end user POV, add a new "force-dvi" audio mode: xrandr --output HDMI1 --set audio force-dvi Note that most users won't need to set this and happily rely on the EDID based DVI auto detection. Reported-by:
Andrea Arcangeli <aarcange@redhat.com> Signed-off-by:
Wu Fengguang <fengguang.wu@intel.com> Signed-off-by:
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- 13 Feb, 2012 3 commits
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Sean Paul authored
This patch replaces the locking from the downclock routines with an assert to ensure the registers are indeed unlocked. Without this patch, pre-SNB devices would lock the registers when downclocking which would cause a WARNING on suspend/resume with downclocking enabled. Note: To hit this bug, you need to have lvds downclocking enabled. Signed-off-by:
Sean Paul <seanpaul@chromium.org> Acked-by:
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Jerome Glisse authored
evergreen and northern island gpu needs more informations for 2D tiling than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace to provide those. The v8 cs checking change to track color view on r6xx/r7xx doesn't affect old userspace as old userspace always emited 0 for this register. v2 fix r6xx/r7xx 2D tiling computation v3 fix r6xx/r7xx height align for untiled surface & add support for tile split on evergreen and newer v4 improve tiling debugging output v5 fix tile split code for evergreen and newer v6 set proper tile split for crtc register v7 fix tile split limit value v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs checking, update safe reg for r600, evergreen and cayman. Evergreen checking need some work around for stencil alignment issues v9 fix tile split value range, fix compressed texture handling and mipmap calculation, allow evergreen check to be silencious in front of current broken userspace (depth/stencil alignment issue) v10 fix eg 3d texture and compressed texture, fix r600 depth array, fix r600 color view computation, add support for evergreen stencil split v11 more verbose debugging in some case Signed-off-by: -
Marek Olšák authored
v2: agd5f: add strmout CS checking, copy_dw register checking v3: agd5f: don't use cs_check_reg() for copy_dw checking as it will incorrectly patch the command stream for certain regs. v4: agd5f: add warning if safe reg check fails for copy_dw v5: agd5f: add stricter checking for 6xx/7xx v6: agd5f: add range checking for copy_dw on eg+, add sx_surface_sync to safe reg list for 7xx. v7: agd5f: add stricter checking for eg+ Signed-off-by:
Marek Olšák <maraeo@gmail.com> Signed-off-by:
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