1. 12 Feb, 2019 17 commits
  2. 11 Feb, 2019 2 commits
  3. 10 Feb, 2019 10 commits
  4. 09 Feb, 2019 11 commits
    • Russell King's avatar
      net: marvell: mvpp2: clear flow control modes in 10G mode · e240b7db
      Russell King authored
      When mvpp2 configures the flow control modes in mvpp2_xlg_config() for
      10G mode, it only ever set the flow control enable bits.  There is no
      mechanism to clear these bits, which means that userspace is unable to
      use standard APIs to disable flow control (the only way is to poke the
      register directly.)
      
      Fix the missing bit clearance to allow flow control to be disabled.
      This means that, by default, as there is no negotiation in 10G modes
      with mvpp2, flow control is now disabled rather than being rx-only.
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e240b7db
    • Andrew Lunn's avatar
      net: phy: Add support for asking the PHY its abilities · efbdfdc2
      Andrew Lunn authored
      Add support for runtime determination of what the PHY supports, by
      adding a new function to the phy driver. The get_features call should
      set the phydev->supported member with the features the PHY supports.
      It is only called if phydrv->features is NULL.
      
      This requires minor changes to pause. The PHY driver should not set
      pause abilities, except for when it has odd cause capabilities, e.g.
      pause cannot be disabled. With this change, phydev->supported already
      contains the drivers abilities, including pause. So rather than
      considering phydrv->features, look at the phydev->supported, and
      enable pause if neither of the pause bits are already set.
      Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
      [hkallweit1@gmail.com: fixed small checkpatch complaint in one comment]
      Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      efbdfdc2
    • Andrew Lunn's avatar
      net: phy: probe the PHY before determining the supported features · 92ed2eb7
      Andrew Lunn authored
      We will soon support asking the PHY at runtime to determine what
      features it supports, rather than forcing it to be compile time.
      But we should probe the PHY first. So probe the phy driver earlier.
      Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      92ed2eb7
    • Heiner Kallweit's avatar
      net: phy: remove unneeded masking of PHY register read results · 50684da7
      Heiner Kallweit authored
      PHY registers are only 16 bits wide, therefore, if the read was
      successful, there's no need to mask out the higher 16 bits.
      Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      50684da7
    • Vakul Garg's avatar
      net/tls: Disable async decrytion for tls1.3 · 8497ded2
      Vakul Garg authored
      Function tls_sw_recvmsg() dequeues multiple records from stream parser
      and decrypts them. In case the decryption is done by async accelerator,
      the records may get submitted for decryption while the previous ones may
      not have been decryted yet. For tls1.3, the record type is known only
      after decryption. Therefore, for tls1.3, tls_sw_recvmsg() may submit
      records for decryption even if it gets 'handshake' records after 'data'
      records. These intermediate 'handshake' records may do a key updation.
      By the time new keys are given to ktls by userspace, it is possible that
      ktls has already submitted some records i(which are encrypted with new
      keys) for decryption using old keys. This would lead to decrypt failure.
      Therefore, async decryption of records should be disabled for tls1.3.
      
      Fixes: 130b392c ("net: tls: Add tls 1.3 support")
      Signed-off-by: default avatarVakul Garg <vakul.garg@nxp.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8497ded2
    • Heiner Kallweit's avatar
      net: phy: disregard "Clause 22 registers present" bit in get_phy_c45_devs_in_pkg · 3b5e74e0
      Heiner Kallweit authored
      Bit 0 in register 1.5 doesn't represent a device but is a flag that
      Clause 22 registers are present. Therefore disregard this bit when
      populating the device list. If code needs this information it
      should read register 1.5 directly instead of accessing the device
      list.
      Because this bit doesn't represent a device don't define a
      MDIO_MMD_XYZ constant, just define a MDIO_DEVS_XYZ constant for
      the flag in the device list bitmap.
      
      v2:
      - make masking of bit 0 more explicit
      - improve commit message
      Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      3b5e74e0
    • David S. Miller's avatar
      Merge branch 'mvpp2-phylink-fixes' · 0abc676e
      David S. Miller authored
      Russell King says:
      
      ====================
      mvpp2 phylink fixes
      
      Having spent a while debugging issues with Sven Auhagen, it appears
      that the mvpp2 network driver's phylink support isn't quite correct.
      
      This series fixes that up, but, despite being tested locally, by
      Sven, and by Antoine, I would prefer it to be applied to net-next
      so that there is time for more people to test before it hits -rc or
      stable backports.
      
      The symptoms were that although PHYs would come up, the GMAC never
      reported that the link was up, or in some cases it did report link
      up but packets would not flow.  Various approaches were tried to
      work around that, such as switching to in-band negotiation from
      PHY mode, but ultimately the problem was in the way mvpp2 was being
      programmed.
      
      This series addresses that by, essentially, making mvpp2 follow the
      same implementation pattern as mvneta: we configure the GMAC in three
      stages:
      
      1) the PHY interface mode
      2) the negotiation advert
      3) the negotiation style
      
      Another issue is that mvpp2 was always taking the link down each time
      its mac_config method was called: this is disruptive when the link is
      already up, and we're just updating settings such as flow control.
      There are some circumstances where we make the call despite there
      being no changes (eg, when phylink is polling a GPIO or using a custom
      link state function.)
      
      This series depends on two previous patches already sent for net-next:
        net: marvell: mvpp2: fix lack of link interrupts
        net: marvell: mvpp2: use phy_interface_mode_is_8023z() helper
      
      There is one last patch which deals with link status interrupts, which
      I'll send separately because I think there's other considerations, but
      that should not hold up this series of patches.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      0abc676e
    • Russell King's avatar
      net: marvell: mvpp2: fix AN restart · a4650477
      Russell King authored
      phylink already limits which interface modes are able to call the
      MACs AN restart function, but in any case, the commentry seems
      incorrect: the AN restart bit does not automatically clear when
      set.  This has been found via manual setting using devmem2, and
      we can observe that the AN does indeed restart and complete, yet
      the AN restart bit remains set.  Explicitly clear the AN restart
      bit.
      Tested-by: default avatarSven Auhagen <sven.auhagen@voleatech.de>
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      a4650477
    • Russell King's avatar
      net: marvell: mvpp2: read correct pause bits · 417f3d08
      Russell King authored
      When reading the pause bits in mac_link_state, mvpp2 was reporting
      the state of the "active pause" bits, which are set when the MAC is
      in pause mode.  This is not what phylink wants - we want the
      negotiated pause state.  Fix the definition so we read the correct
      bits.
      Tested-by: default avatarSven Auhagen <sven.auhagen@voleatech.de>
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      417f3d08
    • Russell King's avatar
      net: marvell: mvpp2: only reprogram what is necessary on mac_config · d14e078f
      Russell King authored
      mac_config() can be called at any point, and the expected behaviour
      from MAC drivers is to only reprogram when necessary - and certainly
      avoid taking the link down on every call.
      
      Unfortunately, mvpp2 does exactly that - it takes the link down, and
      reprograms everything, and then releases the forced-link down.
      
      This is bad, it can cause the link to bounce:
      
      - SFP detects signal, disables LOS indication.
      - SFP code calls into phylink, calling phylink_sfp_link_up() which
        triggers a resolve.
      - phylink_resolve() calls phylink_get_mac_state() and finds the MAC
        reporting link up.
      - phylink wants to configure the pause mode on the MAC, so calls
        phylink_mac_config()
      - mvpp2 takes the link down temporarily, generating a MAC link down
        event followed by another MAC link event.
      - phylink calls mac_link_up() and then processes the MAC link down
        event.
      - phylink_resolve() gets called again, registers the link down, and
        calls mach_link_down() before re-running itself.
      - phylink_resolve() starts again at step 3 above.  This sequence
        repeats.
      
      GMAC versions prior to mvpp2 do not require the link to be taken down
      except when certain link properties (eg, switching between SGMII and
      1000base-X mode, or enabling/disabling in-band negotiation) are
      changed.  Implement this for mvpp2.
      Tested-by: default avatarSven Auhagen <sven.auhagen@voleatech.de>
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      d14e078f
    • Russell King's avatar
      net: marvell: mvpp2: fix stuck in-band SGMII negotiation · 316734fd
      Russell King authored
      It appears that the mvpp22 can get stuck with SGMII negotiation.  The
      symptoms are that in-band negotiation never completes and the partner
      (eg, PHY) never reports SGMII link up, or if it supports negotiation
      bypass, goes into negotiation bypass mode (which will happen when the
      PHY sees that the MAC is alive but gets no response.)
      
      Triggering the PHY end of the link to re-negotiate results in the
      bypass bit clearing on the PHY, and then re-setting - indicating that
      the problem is at the mvpp22 GMAC end.
      
      Asserting the GMAC reset and de-asserting it resolves the issue.
      Arrange to assert the GMAC reset at probe time, and deassert it only
      after we have configured the GMAC for the appropriate mode.  This
      resolves the issue.
      Tested-by: default avatarSven Auhagen <sven.auhagen@voleatech.de>
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      316734fd