- 25 Oct, 2010 40 commits
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Jongsun Han authored
This patch adds the definition for both IRQs and GPIO registers for external interrupts. Signed-off-by:
Jongsun Han <jongsun.han@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Kyungmin Park authored
This patch adds L2 cache initialization code in cpu.c of ARCH_S5PV310. It includes TAG and Data latency, Prefetch, and Power configurations. Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
Changhwan Youn <chaos.youn@samsung.com> Signed-off-by:
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Kyungmin Park authored
Basically, need L2 cache initialize function in ARCH_S5PV310. So it would be better to move it into ARCH_S5PV310 common part. This patch removes L2 cache initialization code at the each board file. Signed-off-by:
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Kyungmin Park authored
This patch adds L2X0 Prefetch and Power control register. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> Signed-off-by:
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Seungwhan Youn authored
This patch moves DMA clock enable functionality into pl330_probe() of plat-samsung/s3c_pl330.c (PL330 DMAC driver) and disable functionality into pl330_remove(). For now according to clock policy of Samsung SoCs' mainline, clocks which are used in the driver should be controlled by each own. Signed-off-by:
Seungwhan Youn <sw.youn@samsung.com> Acked-by:
Jassi Brar <jassi.brar@samsung.com> [kgene.kim@samsung.com: minor title and comment edit] Signed-off-by:
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Seungwhan Youn authored
This patch is matched-up DMA platform device id to its clock id. Signed-off-by:
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Seungwhan Youn authored
This patch modify to DMA operation clock into disable list for default clock setting. Signed-off-by:
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Seungwhan Youn authored
This patch adds DMA operation clock which is disabled as default. Signed-off-by:
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Seungwhan Youn authored
This patch adds DMA operation clock which is disabled as default. Signed-off-by:
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Kukjin Kim authored
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Kukjin Kim authored
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Jassi Brar authored
Audio, Keypad and ADC inherit PCLKD1 clock source. Signed-off-by:
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Chanwoo Choi authored
This patch add cose related to regulator. To control powre consumeption have registered the voltage consumer of WM8994 to the regulator framework. Additionally, I explain the constraints of the regulator of WM8994 codec. All these consumer supply of WM8994 codec connected the regulator(VCC_1.8V) on a circuit diagram. "VCC_1.8V" regulator is always enabled, because it is used to many devices on Goni/Aquila board. This is required especially when there are many devices physically attached to "VCC_1.8V" and some of they did not "register" as consumers to "VCC_1.8V". "VCC_1.8V" might be turned off by those who are registered while "unregistered" are still active Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:
Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by:
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Chanwoo Choi authored
This patch add initialization code of audio and I2S platform drivers to Goni and Aquila board. Signed-off-by:
Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by:
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Chanwoo Choi authored
This patch the I2C board information for the WM8994 used in the Goni/Aquila as audio codec and adds the I2C platform drivers. Signed-off-by:
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Jongpill Lee authored
This patch adds GPIOlib support for S5PV310 and S5PC210. Signed-off-by:
Jongpill Lee <boyko.lee@samsung.com> Signed-off-by:
Sangbeom Kim <sbkim73@samsung.com> [kgene.kim@samsung.com: Fix NR_IRQS] Signed-off-by:
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Jongpill Lee authored
This patch adds initial map for GPIO2 and GPIO3. S5PV310/S5PC210 has separated GPIO1, GPIO2 and GPIO3. Signed-off-by:
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Jongpill Lee authored
This patch updates MAX_COMBINER_NR from 39 to 40 because S5PV310 need 39th combiner for including EINT16_31. Signed-off-by:
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Seungwhan Youn authored
This patch adds warning about changing EPLL rate to notice that other driver that controls H/W, which is using EPLL, will has unknown effects by this EPLL rate change. Signed-off-by:
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Seungwhan Youn authored
This patch adds EPLL specific clock get_rate/set_rate operations on S5PV210. Signed-off-by:
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Seungwhan Youn authored
This patch fix wrong EPLL getting on setup clocks on S5PV210. Signed-off-by:
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Seungwhan Youn authored
S5P Samsung SoCs has a EPLL to support various PLL clock sources for other H/W blocks. Until now, to control EPLL, each of SoCs make their own functions in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and 'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move these duplicated codes to common EPLL functions that use platform wide. Signed-off-by:
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Seungwhan Youn authored
This patch adds audio clocks(SCLK_AUDIO{0,1,2} and SCLK_AUDIO) to be initial as a sysclk on boot-time. Signed-off-by: -
Seungwhan Youn authored
This patch add SCLK_SPDIF clock to support source clock of S/PDIF on S5PV210. Signed-off-by:
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Seungwhan Youn authored
This patch add S/PDIF platform device to support S/PDIF PCM audio on S5PV210. Signed-off-by:
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Seungwhan Youn authored
This patch add SCLK_SPDIF clock to support source clock of S/PDIF on S5PC100. Signed-off-by:
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Seungwhan Youn authored
This patch modify SCLK_AUDIO{0,1,2} to be initial as sysclks on boot-time. Signed-off-by: -
Seungwhan Youn authored
This patch add S/PDIF platform device to support S/PDIF PCM audio on S5PC100. Signed-off-by:
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Mark Brown authored
Since it's exported we should make sure we're using the prototype others see. Signed-off-by:
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Mark Brown authored
Since it's exported we should make sure we're using the prototype others see. Signed-off-by:
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Jaecheol Lee authored
This patch adds ARCH_HAS_CPUFREQ in arch/arm/Kconfig for S5PV210, and updates mach-s5pv210/Makefile for supporting build CPUFREQ driver. Signed-off-by:
Jaecheol Lee <jc.lee@samsung.com> Signed-off-by:
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Jaecheol Lee authored
This patch adds CPUFREQ driver for supporting DFS(Dynamic Frequency Scaling). Signed-off-by:
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Jaecheol Lee authored
This patch adds some CMU(Clock Management Unit) registers for supporting CPUFREQ and some drivers. Signed-off-by:
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Jaecheol Lee authored
This patch adds MOUT_DMC0 and SCLK_DMC0 for checking the dmc0 clock in CPUFREQ driver. Signed-off-by:
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Jaecheol Lee authored
Current fout_apll has fixed rate value. So CPUFREQ driver gets incorrect value when finding current CPU frequency. Because some operation level need to change APLL. Added get_rate function for fout_apll can give correct frequency value when calling get_rate function. Signed-off-by:
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Kyungmin Park authored
S5PV310 and S5PC210 support more I2C devices than previous SoCs. Add the device support code for them. Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
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Kyungmin Park authored
S5PV310 and S5PC210 support total 8 (+ 1 dedicated for HDMI) I2C devices. Signed-off-by:
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Kyungmin Park authored
The name of the I2C2 and I2C3 interrupt should be IIC2 and IIC3 instead of CAN0 and CAN1. Signed-off-by:
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Kukjin Kim authored
This patch changes I2C2 and I2C3 interrupt name from IRQ_CANX to IRQ_IICX according other SoCs' I2C interrupt naming rule. Signed-off-by: -
Kukjin Kim authored
Basically S5P SoCs use the Samsung common VA address mapping where plat-samsung and use plat-s5p's mapping also. The later is a little mess. So this patch cleans it up. Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by:
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