1. 18 Jul, 2012 5 commits
    • Chris Metcalf's avatar
      tile pci: enable IOMMU to support DMA for legacy devices · 41bb38fc
      Chris Metcalf authored
      This change uses the TRIO IOMMU to map the PCI DMA space and physical
      memory at different addresses.  We also now use the dma_mapping_ops
      to provide support for non-PCI DMA, PCIe DMA (64-bit) and legacy PCI
      DMA (32-bit).  We use the kernel's software I/O TLB framework
      (i.e. bounce buffers) for the legacy 32-bit PCI device support since
      there are a limited number of TLB entries in the IOMMU and it is
      non-trivial to handle indexing, searching, matching, etc.  For 32-bit
      devices the performance impact of bounce buffers should not be a concern.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      41bb38fc
    • Chris Metcalf's avatar
      arch/tile: enable ZONE_DMA for tilegx · eef015c8
      Chris Metcalf authored
      This is required for PCI root complex legacy support and USB OHCI root
      complex support.  With this change tilegx now supports allocating memory
      whose PA fits in 32 bits.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      eef015c8
    • Chris Metcalf's avatar
      tilegx pci: support I/O to arbitrarily-cached pages · bbaa22c3
      Chris Metcalf authored
      The tilegx PCI root complex support (currently only in linux-next)
      is limited to pages that are homed on cached in the default manner,
      i.e. "hash-for-home".  This change supports delivery of I/O data to
      pages that are cached in other ways (locally on a particular core,
      uncached, user-managed incoherent, etc.).
      
      A large part of the change is supporting flushing pages from cache
      on particular homes so that we can transition the data that we are
      delivering to or from the device appropriately.  The new homecache_finv*
      routines handle this.
      
      Some changes to page_table_range_init() were also required to make
      the fixmap code work correctly on tilegx; it hadn't been used there
      before.
      
      We also remove some stub mark_caches_evicted_*() routines that
      were just no-ops anyway.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      bbaa22c3
    • Paul Bolle's avatar
      tile: remove unused header · 3e219b91
      Paul Bolle authored
      Nothing includes memprof.h. Nothing uses the macros it defines. It seems
      it is just a remnant of the proposed memprof functionality, which got
      dropped before the Tilera architecture got added to the tree. This
      header can safely be removed.
      Signed-off-by: default avatarPaul Bolle <pebolle@tiscali.nl>
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      3e219b91
    • Chris Metcalf's avatar
      arch/tile: tilegx PCI root complex support · 12962267
      Chris Metcalf authored
      This change implements PCIe root complex support for tilegx using
      the kernel support layer for accessing the TRIO hardware shim.
      
      Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> [changes in 07487f3]
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      12962267
  2. 11 Jul, 2012 6 commits
    • Chris Metcalf's avatar
      arch/tile: provide kernel support for the tilegx TRIO shim · bce5bbbb
      Chris Metcalf authored
      Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip
      hardware.  This hardware implements the PCIe interface for tilegx;
      the driver changes to use TRIO for PCIe are in a subsequent commit.
      
      The change is layered on top of the tilegx GXIO IORPC subsystem.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      bce5bbbb
    • Chris Metcalf's avatar
      arch/tile: break out the "csum a long" function to <asm/checksum.h> · 10104a1a
      Chris Metcalf authored
      This makes it available to the tilegx network driver.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      10104a1a
    • Chris Metcalf's avatar
      arch/tile: provide kernel support for the tilegx mPIPE shim · 4875f69f
      Chris Metcalf authored
      The TILE-Gx chip includes a packet-processing network engine called
      mPIPE ("Multicore Programmable Intelligent Packet Engine").  This
      change adds support for using the mPIPE engine from within the
      kernel.  The engine has more functionality than is exposed here,
      but to keep the kernel code and binary simpler, this is a subset
      of the full API designed to enable standard Linux networking only.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      4875f69f
    • Chris Metcalf's avatar
      arch/tile: common DMA code for the GXIO IORPC subsystem · 63697980
      Chris Metcalf authored
      The dma_queue support is used by both the mPipe (networking)
      and Trio (PCI) hardware shims on tilegx.  This common code is
      selected when either of those drivers is built.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      63697980
    • Chris Metcalf's avatar
      arch/tile: support MMIO-based readb/writeb etc. · 44e56967
      Chris Metcalf authored
      Add support for MMIO read/write on tilegx to support GXIO IORPC access.
      Similar to the asm-generic version, but we include memory fences on
      the writes to be conservative.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      44e56967
    • Chris Metcalf's avatar
      arch/tile: introduce GXIO IORPC framework for tilegx · 37b82b5d
      Chris Metcalf authored
      The GXIO I/O RPC subsystem handles exporting I/O hardware resources to
      Linux and to applications running under Linux.
      
      For instance, memory which is made available for I/O DMA must be mapped
      by an I/O TLB; that means that such memory must be locked down by Linux,
      so that it is not swapped or otherwise reused, as long as those I/O
      TLB entries are active. Similarly, configuring direct hardware access
      introduces new validation requirements. If a user application registers
      memory, Linux must ensure that the supplied virtual addresses are valid,
      and turn them into client physical addresses. Similarly, when Linux then
      supplies those client physical addresses to the Tilera hypervisor, it
      must in turn validate those before turning them into the real physical
      addresses which are required by the hardware.
      
      To the extent that these sorts of activities were required on previous
      TILE architecture processors, they were implemented in a device-specific
      fashion. This meant that every I/O device had its own Tilera hypervisor
      driver, its own Linux driver, and in some cases its own user-level
      library support. There was a large amount of more-or-less functionally
      identical code in different places, particularly in the different Linux
      drivers. For TILE-Gx, this support has been generalized into a common
      framework, known as the I/O RPC framework or just IORPC.
      
      The two "gxio" directories (one for headers, one for sources) start
      with just a few files in each with this infrastructure commit, but
      after adding support for the on-board I/O shims for networking, PCI,
      USB, crypto, compression, I2CS, etc., there end up being about 20 files
      in each directory.
      
      More information on the IORPC framework is in the <hv/iorpc.h> header,
      included in this commit.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      37b82b5d
  3. 08 Jul, 2012 3 commits
  4. 07 Jul, 2012 2 commits
    • Linus Torvalds's avatar
      Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm · cd6407fe
      Linus Torvalds authored
      Pull ARM fixes from Russell King:
       "Last merge window, we had some updates from Al cleaning up the signal
        restart handling.  These have caused some problems on ARM, and while
        Al has some fixes, we have some concerns with Al's patches but we've
        been unsuccesful with discussing this.
      
        We have got to the point where we need to do something, and we've
        decided that the best solution is to revert the appropriate commits
        until Al is able to reply to us.
      
        Also included here are four patches to fix warnings that I've noticed
        in my build system, and one fix for kprobes test code."
      
      * 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
        ARM: fix warning caused by wrongly typed arm_dma_limit
        ARM: fix warnings about atomic64_read
        ARM: 7440/1: kprobes: only test 'sub pc, pc, #1b-2b+8-2' on ARMv6
        ARM: 7441/1: perf: return -EOPNOTSUPP if requested mode exclusion is unavailable
        ARM: 7443/1: Revert "new way of handling ERESTART_RESTARTBLOCK"
        ARM: 7442/1: Revert "remove unused restart trampoline"
        ARM: fix set_domain() macro
        ARM: fix mach-versatile/pci.c warning
      cd6407fe
    • Andy Lutomirski's avatar
      security: Minor improvements to no_new_privs documentation · c540521b
      Andy Lutomirski authored
      The documentation didn't actually mention how to enable no_new_privs.
      This also adds a note about possible interactions between
      no_new_privs and LSMs (i.e. why teaching systemd to set no_new_privs
      is not necessarily a good idea), and it references the new docs
      from include/linux/prctl.h.
      Suggested-by: default avatarRob Landley <rob@landley.net>
      Signed-off-by: default avatarAndy Lutomirski <luto@amacapital.net>
      Acked-by: default avatarKees Cook <keescook@chromium.org>
      Signed-off-by: default avatarJames Morris <james.l.morris@oracle.com>
      c540521b
  5. 06 Jul, 2012 11 commits
  6. 05 Jul, 2012 13 commits