1. 24 Apr, 2019 9 commits
    • Andrew Murray's avatar
      arm64: KVM: Enable VHE support for :G/:H perf event modifiers · 435e53fb
      Andrew Murray authored
      With VHE different exception levels are used between the host (EL2) and
      guest (EL1) with a shared exception level for userpace (EL0). We can take
      advantage of this and use the PMU's exception level filtering to avoid
      enabling/disabling counters in the world-switch code. Instead we just
      modify the counter type to include or exclude EL0 at vcpu_{load,put} time.
      
      We also ensure that trapped PMU system register writes do not re-enable
      EL0 when reconfiguring the backing perf events.
      
      This approach completely avoids blackout windows seen with !VHE.
      Suggested-by: default avatarChristoffer Dall <christoffer.dall@arm.com>
      Signed-off-by: default avatarAndrew Murray <andrew.murray@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      435e53fb
    • Andrew Murray's avatar
      arm64: KVM: Enable !VHE support for :G/:H perf event modifiers · 3d91befb
      Andrew Murray authored
      Enable/disable event counters as appropriate when entering and exiting
      the guest to enable support for guest or host only event counting.
      
      For both VHE and non-VHE we switch the counters between host/guest at
      EL2.
      
      The PMU may be on when we change which counters are enabled however
      we avoid adding an isb as we instead rely on existing context
      synchronisation events: the eret to enter the guest (__guest_enter)
      and eret in kvm_call_hyp for __kvm_vcpu_run_nvhe on returning.
      Signed-off-by: default avatarAndrew Murray <andrew.murray@arm.com>
      Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      3d91befb
    • Andrew Murray's avatar
      arm64: arm_pmu: Add !VHE support for exclude_host/exclude_guest attributes · d1947bc4
      Andrew Murray authored
      Add support for the :G and :H attributes in perf by handling the
      exclude_host/exclude_guest event attributes.
      
      We notify KVM of counters that we wish to be enabled or disabled on
      guest entry/exit and thus defer from starting or stopping events based
      on their event attributes.
      
      With !VHE we switch the counters between host/guest at EL2. We are able
      to eliminate counters counting host events on the boundaries of guest
      entry/exit when using :G by filtering out EL2 for exclude_host. When
      using !exclude_hv there is a small blackout window at the guest
      entry/exit where host events are not captured.
      Signed-off-by: default avatarAndrew Murray <andrew.murray@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      d1947bc4
    • Andrew Murray's avatar
      arm64: KVM: Add accessors to track guest/host only counters · eb41238c
      Andrew Murray authored
      In order to effeciently switch events_{guest,host} perf counters at
      guest entry/exit we add bitfields to kvm_cpu_context for guest and host
      events as well as accessors for updating them.
      
      A function is also provided which allows the PMU driver to determine
      if a counter should start counting when it is enabled. With exclude_host,
      we may only start counting when entering the guest.
      Signed-off-by: default avatarAndrew Murray <andrew.murray@arm.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      eb41238c
    • Andrew Murray's avatar
      arm64: KVM: Encapsulate kvm_cpu_context in kvm_host_data · 630a1685
      Andrew Murray authored
      The virt/arm core allocates a kvm_cpu_context_t percpu, at present this is
      a typedef to kvm_cpu_context and is used to store host cpu context. The
      kvm_cpu_context structure is also used elsewhere to hold vcpu context.
      In order to use the percpu to hold additional future host information we
      encapsulate kvm_cpu_context in a new structure and rename the typedef and
      percpu to match.
      Signed-off-by: default avatarAndrew Murray <andrew.murray@arm.com>
      Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      630a1685
    • Andrew Murray's avatar
      arm64: arm_pmu: Remove unnecessary isb instruction · 21bb0ebf
      Andrew Murray authored
      The armv8pmu_enable_event_counter function issues an isb instruction
      after enabling a pair of counters - this doesn't provide any value
      and is inconsistent with the armv8pmu_disable_event_counter.
      
      In any case armv8pmu_enable_event_counter is always called with the
      PMU stopped. Starting the PMU with armv8pmu_start results in an isb
      instruction being issued prior to writing to PMCR_EL0.
      
      Let's remove the unnecessary isb instruction.
      Signed-off-by: default avatarAndrew Murray <andrew.murray@arm.com>
      Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      21bb0ebf
    • Amit Daniel Kachhap's avatar
      KVM: arm64: Add capability to advertise ptrauth for guest · a243c16d
      Amit Daniel Kachhap authored
      This patch advertises the capability of two cpu feature called address
      pointer authentication and generic pointer authentication. These
      capabilities depend upon system support for pointer authentication and
      VHE mode.
      
      The current arm64 KVM partially implements pointer authentication and
      support of address/generic authentication are tied together. However,
      separate ABI requirements for both of them is added so that any future
      isolated implementation will not require any ABI changes.
      Signed-off-by: default avatarAmit Daniel Kachhap <amit.kachhap@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Christoffer Dall <christoffer.dall@arm.com>
      Cc: kvmarm@lists.cs.columbia.edu
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      a243c16d
    • Amit Daniel Kachhap's avatar
      KVM: arm64: Add userspace flag to enable pointer authentication · a22fa321
      Amit Daniel Kachhap authored
      Now that the building blocks of pointer authentication are present, lets
      add userspace flags KVM_ARM_VCPU_PTRAUTH_ADDRESS and
      KVM_ARM_VCPU_PTRAUTH_GENERIC. These flags will enable pointer
      authentication for the KVM guest on a per-vcpu basis through the ioctl
      KVM_ARM_VCPU_INIT.
      
      This features will allow the KVM guest to allow the handling of
      pointer authentication instructions or to treat them as undefined
      if not set.
      
      Necessary documentations are added to reflect the changes done.
      Reviewed-by: default avatarDave Martin <Dave.Martin@arm.com>
      Signed-off-by: default avatarAmit Daniel Kachhap <amit.kachhap@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Christoffer Dall <christoffer.dall@arm.com>
      Cc: kvmarm@lists.cs.columbia.edu
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      a22fa321
    • Mark Rutland's avatar
      KVM: arm/arm64: Context-switch ptrauth registers · 384b40ca
      Mark Rutland authored
      When pointer authentication is supported, a guest may wish to use it.
      This patch adds the necessary KVM infrastructure for this to work, with
      a semi-lazy context switch of the pointer auth state.
      
      Pointer authentication feature is only enabled when VHE is built
      in the kernel and present in the CPU implementation so only VHE code
      paths are modified.
      
      When we schedule a vcpu, we disable guest usage of pointer
      authentication instructions and accesses to the keys. While these are
      disabled, we avoid context-switching the keys. When we trap the guest
      trying to use pointer authentication functionality, we change to eagerly
      context-switching the keys, and enable the feature. The next time the
      vcpu is scheduled out/in, we start again. However the host key save is
      optimized and implemented inside ptrauth instruction/register access
      trap.
      
      Pointer authentication consists of address authentication and generic
      authentication, and CPUs in a system might have varied support for
      either. Where support for either feature is not uniform, it is hidden
      from guests via ID register emulation, as a result of the cpufeature
      framework in the host.
      
      Unfortunately, address authentication and generic authentication cannot
      be trapped separately, as the architecture provides a single EL2 trap
      covering both. If we wish to expose one without the other, we cannot
      prevent a (badly-written) guest from intermittently using a feature
      which is not uniformly supported (when scheduled on a physical CPU which
      supports the relevant feature). Hence, this patch expects both type of
      authentication to be present in a cpu.
      
      This switch of key is done from guest enter/exit assembly as preparation
      for the upcoming in-kernel pointer authentication support. Hence, these
      key switching routines are not implemented in C code as they may cause
      pointer authentication key signing error in some situations.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      [Only VHE, key switch in full assembly, vcpu_has_ptrauth checks
      , save host key in ptrauth exception trap]
      Signed-off-by: default avatarAmit Daniel Kachhap <amit.kachhap@arm.com>
      Reviewed-by: default avatarJulien Thierry <julien.thierry@arm.com>
      Cc: Christoffer Dall <christoffer.dall@arm.com>
      Cc: kvmarm@lists.cs.columbia.edu
      [maz: various fixups]
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      384b40ca
  2. 23 Apr, 2019 1 commit
  3. 18 Apr, 2019 14 commits
  4. 02 Apr, 2019 1 commit
    • Marc Zyngier's avatar
      arm64: KVM: Fix system register enumeration · 5d8d4af2
      Marc Zyngier authored
      The introduction of the SVE registers to userspace started with a
      refactoring of the way we expose any register via the ONE_REG
      interface.
      
      Unfortunately, this change doesn't exactly behave as expected
      if the number of registers is non-zero and consider everything
      to be an error. The visible result is that QEMU barfs very early
      when creating vcpus.
      
      Make sure we only exit early in case there is an actual error, rather
      than a positive number of registers...
      
      Fixes: be25bbb3 ("KVM: arm64: Factor out core register ID enumeration")
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      5d8d4af2
  5. 29 Mar, 2019 15 commits