Commits · 464ab91ac5f1765c758722a1c298873795773a2f · nexedi / linux

01 Jul, 2020 40 commits

drm/amdgpu: Enable DM block for DCN3 · 464ab91a

Bhawanpreet Lakha authored May 21, 2020

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

464ab91a

drm/amd/display: Remove Unused Registers · 7f3e2919

Bhawanpreet Lakha authored May 21, 2020

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

7f3e2919

drm/amd/display: Handle RGBE_ALPHA Pixel Format · fb625e1b

Bhawanpreet Lakha authored May 21, 2020

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

fb625e1b

drm/amd/display: Init function tables for DCN3 · c5c76abd

Bhawanpreet Lakha authored May 25, 2020

Initilize function tables for hw programing
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

c5c76abd

drm/amd/display: Add DCN3 VPG · 3c10f4fb

Bhawanpreet Lakha authored May 25, 2020

Video Package generator.

used to prepare avi info, DP info etc
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3c10f4fb

drm/amd/display: Add DCN3 AFMT · 73de3de5

Bhawanpreet Lakha authored May 21, 2020

Audio formating

Audio related code for setup/control
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

73de3de5

drm/amd/display: Add DCN3 Command Table Helpers · 330fa233

Bhawanpreet Lakha authored May 21, 2020

-Handle DCN3 cases for bios parser and command tables
-Add command function tables for DCN3
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

330fa233

drm/amd/display: Add DCN3 Resource · 5dba4991

Bhawanpreet Lakha authored May 21, 2020

Add support for managing resources for DCN3
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

5dba4991

drm/amd/display: Add DCN3 Support in DM (v2) · 79037324

Bhawanpreet Lakha authored May 21, 2020

Handle DCN3 in amdgpu_dm

v2: fix num_pkrs handling
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

79037324

drm/amd/display: Add DCN3 HWSEQ · d99f1387

Bhawanpreet Lakha authored May 21, 2020

Add HW sequence programing for DCN3
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

d99f1387

drm/amd/display: Add DCN3 DMUB · 5baebf61

Bhawanpreet Lakha authored May 29, 2020

DMUB (Display Micro-Controller Unit)

Used to read/write regs
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

5baebf61

drm/amd/display: Add DCN3 GPIO · 666ed8bf

Bhawanpreet Lakha authored May 21, 2020

Add support to program GPIO HW block
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

666ed8bf

drm/amd/display: Add DCN3 IRQ · 21f4809a

Bhawanpreet Lakha authored May 21, 2020

Add IWQ services for DCN3,

This allows us to create/init and manage irqs for DCN3
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

21f4809a

drm/amd/display: Add DCN3 DML · 6725a88f

Bhawanpreet Lakha authored May 21, 2020

Add support for DML(Display mode library) for bandwidth calculations
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

6725a88f

drm/amd/display: Add DCN3 DWB · 8993dee0

Bhawanpreet Lakha authored May 21, 2020

Add support to program the DCN3 DWB (Display Writeback)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |                     ^
        v                     |
    +--------+            +--------+
    |  DPP   |            |  DWB   |
    +--------+            +--------+
        |
        v                      ^
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+                  |
    |  OPP  |                  |
    +-------+                  |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

8993dee0

drm/amd/display: Add DCN3 MMHUBHUB · 4898dc48

Bhawanpreet Lakha authored May 21, 2020

Add support to program the DCN3 MMHUBBUB (Multimedia HUB interface)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

4898dc48

drm/amd/display: Add DCN3 HUBP · db7b0216

Bhawanpreet Lakha authored May 21, 2020

Add support to program the DCN3 HUBP (Display to data fabric interface
pipe)

HW Blocks:

 +--------++------+
 | HUBBUB || HUBP |
 +--------++------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

db7b0216

drm/amd/display: Add DCN3 HUBHUB · 8f712e3e

Bhawanpreet Lakha authored May 21, 2020

Add support to program the HUBBUB (DCN memory HUB interface)

HW Blocks:

 +--------+
 | HUBBUB |
 +--------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

8f712e3e

drm/amd/display: Add DCN3 DPP · 03f54d7d

Bhawanpreet Lakha authored May 21, 2020

Add support to program the DCN3 DPP (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

03f54d7d

drm/amd/display: Add DCN3 MPC · b708205f

Bhawanpreet Lakha authored May 21, 2020

Add support to program the DCN3 MPC (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

b708205f

drm/amd/display: Add DCN3 OPP header · 8ea13e52

Bhawanpreet Lakha authored May 22, 2020

Add support to program the DCN3 OPP (Output Plane Processing)

HW Blocks:

    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

8ea13e52

drm/amd/display: Add DCN3 OPTC · 64e7f91e

Bhawanpreet Lakha authored May 21, 2020

Add support for programming the DCN3 OPTC (Output Timing Controller)

HW Blocks:

    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

64e7f91e

drm/amd/display: Add DCN3 DCCG · 2a3a0d5d

Bhawanpreet Lakha authored May 21, 2020

Add programming of the DCCG (Display Controller Clock Generator)
block:

HW Blocks:

    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2a3a0d5d

drm/amd/display: Add DCN3 CLK_MGR · 4d55b0dd

Bhawanpreet Lakha authored May 21, 2020

Adds support for handling of clocking relevant to the DCN3 block
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

4d55b0dd

drm/amd/display: Add DCN3 DIO · be547111

Bhawanpreet Lakha authored May 22, 2020

Add support for the DIO (Display IO)  block of DCN3, which entails our
stream and link encoders.

HW Blocks:

    +--------+
    |  DIO   |
    +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

be547111

drm/amd/display: Add DCN3 chip ids · 7c40270b

Bhawanpreet Lakha authored May 21, 2020

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

7c40270b

drm/amdgpu: bypass tmr when reserve c2p memory · 2c6e83a1

Likun Gao authored May 26, 2020

C2P memory reserved should not in tmr memory range.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2c6e83a1

drm/amdgpu: remove unnecessary check for mem train · 72d208c2

Likun Gao authored May 22, 2020

a.Check whether mem train support when try to reserve related memory.
b.Remove ASIC check and atom firmware table version check as the check
of firmware capability is enough to achieve that purpose.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

72d208c2

drm/amdgpu: support memory training for sienna_cichlid · 0a4fa83c

Likun Gao authored May 21, 2020

Add memory training support for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

0a4fa83c

drm/amdgpu: reserve fb according to return value from vbios · 83d7f66a

Likun Gao authored May 21, 2020

Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards
for all the use cases (IP discovery/G6 memory
training/profiling/diagnostic data.etc), otherwise, fallback to legacy
approach to check and reserve tmr block for ip discovery data and G6
memory training data respectively
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

83d7f66a

drm/amd/powerplay: let PMFW to handle the features disablement on BACO in V2 · 4c301044

Evan Quan authored May 29, 2020

For Sienna_Cichlid, PMFW will handle the features disablement on BACO in. No
need to have driver stepped in.

V2: limit this for baco really
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

4c301044

drm/amd/powerplay: drop sienna_cichlid hardcode of using pptable · e2c14b2c

Likun Gao authored May 18, 2020

Drop the hardcode of sienna_cichlid which will force to use softpptable,
so that it can use pptable on vbios once the value of pp_table_id get
from vbios is 0.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

e2c14b2c

drm/amd/powerplay: update smu function for sienna_cichlid · 40d3b8db

Likun Gao authored May 13, 2020

Add function to check whether baco is support for sienna cichlid.
Remove fucntion of get clock by type with latency as it will not be
called.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

40d3b8db

drm/amdgpu: update golden setting for sienna_cichlid · 04af75ef

Likun Gao authored May 08, 2020

Update golden setting for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

04af75ef

drm/amdgpu/psp: support for loading PSP SPL fw · 70509057

Likun Gao authored May 06, 2020

Add support for loading SPL firmware.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

70509057

drm/amdgpu/psp: initialization PSP SPL fw · 43a188e0

Likun Gao authored May 06, 2020

Support for psp firmware header version v1_3 initialization and
information print.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

43a188e0

drm/amdgpu/psp: add structure to support PSP SPL · 390d59be

Likun Gao authored May 06, 2020

Add support for PSP SPL (Security patch level) table to support
anti-rollback of FW loaded by Trusted OS.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

390d59be

drm/amd/powerplay: show gfxclk=0 in gfxoff state · ba818620

Kenneth Feng authored May 07, 2020

The instant retrieved gfxclk value should be 0 in gfxoff state.
This can be fetched with gfxoff enabled.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

ba818620

drm/amdgpu: enable gfxoff for sienna_cichlid · e0da123a

Likun Gao authored May 29, 2020

Enable GFXOFF for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

e0da123a

drm/amd/amdgpu: disable gfxoff to retrieve gfxclk · 258d290c

Likun Gao authored Apr 20, 2020

For Sienna_Cichlid, GFXOFF state puts gfx dpm into standby mode, then the
gfxclk can't be retireved.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

258d290c