Currently, x86_64 and ia64 arches do not clear the corresponding bits in
the node's cpumask when a cpu goes down or cpu bring up is cancelled.  This
is buggy since there are pieces of common code where the cpumask is checked
in the cpu down code path to decide on things (like in the slab down path).
 PPC does the right thing, but x86_64 and ia64 don't (This was the reason
Sonny hit upon a slab bug during cpu offline on ppc and could not reproduce
on other arches).  This patch fixes it for x86_64.  I won't attempt ia64 as
I cannot test it.

Credit for spotting this should go to Alok.

(akpm: this was applied, then reverted.  But it's OK now because we now use
for_each_cpu() in the right places).
Signed-off-by: Alok N Kataria <alokk@calsoftinc.com>
Signed-off-by: Ravikiran Thirumalai <kiran@scalex86.org>
Signed-off-by: Shai Fultheim <shai@scalex86.org>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

- Remove unneeded bio_get() which would cause a bio leak

- Writing doesn't dirty pages.  Reading dirties pages.

- We should dirty the pages after the IO completion, not before

(Busy-waiting for disk I/O completion isn't very polite.)
Signed-off-by: Pavel Machek <pavel@suse.cz>
Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

drivers/base/bus.c:166: warning: `driver_attr_unbind' defined but not used
drivers/base/bus.c:194: warning: `driver_attr_bind' defined but not used

Looks like these two attributes and supporting functions want to be
#ifdef HOTPLUG'd
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

The softirq rq completion handler needs to save/restore interrupt flags
appropriately.
Signed-off-by: Jens Axboe <axboe@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Fix wrong '!' in bad apic fix

I forgot to remove the ! when moving the code from x86-64 to i386 x86-64
tested !disable_apic, but of course for cpu_has_apic it shouldn't be
negated.

Credit goes to Jan Beulich for spotting it with eagle eyes.

Cc: Jan Beulich <jbeulich@novell.com>
Cc: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

    
The reset state is undefined and some firmware doesn't clear this bit
possibly resulting in crashes on entry into userland.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
I've noticed that PCI clock was incorrectly reported as 66 MHz while being
mere 33 MHz on RBTX4937 board -- this was due to the different encoding of
the PCI divisor field in CCFG register between TX4927 and TX4937 chips...
    
Also, RBTX49x7 was printed out as a CPU name (e.g., "CPU is RBTX4937");
and some debug printk() were duplicating each other...
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
If mfc0 $12 follows store and the mfc0 is last instruction of a
page and fetching the next instruction causes TLB miss, the result
of the mfc0 might wrongly contain EXL bit.
    
ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
    
Workaround: mask EXL bit of the result or place a nop before mfc0.  It
doesn't harm to always clear those bits, so we change the code to do so.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
Very much to my surprise Fuxin Zhang reports this is all it takes to get
the kernel to work for page sizes larger than 4kB.  This also paves the
way for support for the R6000 and R8000 which don't support 4kB page size.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

From Franck Bui-Huu <vagabon.xyz@gmail.com> with modifications by me.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
I'm pretty sure that the CKSEG0 bits are wrong, but I did need to
cover that region - because the SB-1 kernel links at 0xffffffff80100000
or so, disassembly and printing static variables don't work unless the
debugger can read that region.
Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
From: Kaj-Michael Lang <milang@tal.org>
    
In ip22-setup.c the checks for serial/graphics console logic does
not check if ARCS console=g but the machine is using serial console, as
it does if no keyboard is attached.
    
This patch adds a check if ConsoleOut is serial. There might also be
support for other graphics than Newport soon...
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
It looks glibc's pow() assumes an unary '-' operation for any number
(including NaNs) always inverts its sign bit (though IEEE754 does not
specify the sign bit for NaNs).  This patch make the kernel math-emu
emulates real MIPS neg.[ds] instruction.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
This fixes sparse warnings 'dereference of noderef expression'.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
fls was the only called of flz, so fold flz into fls, same for the
__ilog2 call.  Delete the now unused flz function.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
It always left the assembler in reorder mode possibly causing disaster.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
Adding -mmad is not usable since over half a decade in gcc and when
fixed the proper -march option values should enable the use of the
mad, madu and mul instructions of the R5500, RM5200, RM7000 and RM9000
families.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
Build blast_xxx, blast_xxx_page, blast_xxx_page_indexed from template.
Easier to maintaina and saves 300 lines.  Generated code should be
unchanged.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
Patch courtesy of Emily Postnews ;-)
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
AMD Au1200 SOC just doesn't have UART3, so KGDB won't even compile for it
as is, here's the fix to make KGDB use UART1.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
Fix a really old buglet in AMD Au1xx0 restart code: instead of
modifying the whole CP0 Config.K0 field to 010b (meaning KSEG0 uncached)
before flushing the caches and resetting a board, it only sets bit 1 of that
reg. which is effectively a NOP since Config.K0 == 011b as the kernel sets it
up (which is also its default value for Au1xx0).
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

    
Fix the #define's for TX4927/37 timer reg's to match the datasheets (those
Signed-off-by: Konstantin Baydarov <kbaidarov@mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Mark Mason <mason@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Mark Mason <mason@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>