1. 05 May, 2016 3 commits
  2. 04 May, 2016 3 commits
  3. 03 May, 2016 5 commits
  4. 02 May, 2016 4 commits
  5. 29 Apr, 2016 19 commits
  6. 28 Apr, 2016 6 commits
    • Ville Syrjälä's avatar
      drm/i915: Fix comments about GMBUSFREQ register · b5d99ff9
      Ville Syrjälä authored
      The comment about GMBUSFREQ is confused. The spec actually explains
      the 4MHz thing perfectly by noting that the 4MHz divider values is
      actually just bits [9:2] not [9:0], hence the divide by 1000 correct.
      Replace the confused note with a quote from the spec, and eliminate
      the duplicated comment that snuck in.
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1461689194-6079-4-git-send-email-ville.syrjala@linux.intel.comReviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
      b5d99ff9
    • Ville Syrjälä's avatar
      drm/i915: Use cached cdclk value in i915_audio_component_get_cdclk_freq() · 1033f92e
      Ville Syrjälä authored
      No point in reading the cdclk out from the hardware every single time
      since we have it cached already. Just return the cached value to the
      audio driver.
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1461689194-6079-3-git-send-email-ville.syrjala@linux.intel.comReviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
      1033f92e
    • Ville Syrjälä's avatar
      drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency · 7f1052a8
      Ville Syrjälä authored
      Update CDCLK_FREQ on BDW after changing the cdclk frequency. Not sure
      if this is a late addition to the spec, or if I simply overlooked this
      step when writing the original code.
      
      This is what Bspec has to say about CDCLK_FREQ:
      "Program this field to the CD clock frequency minus one. This is used to
       generate a divided down clock for miscellaneous timers in display."
      
      And the "Broadwell Sequences for Changing CD Clock Frequency" section
      clarifies this further:
      "For CD clock 337.5 MHz, program 337 decimal.
       For CD clock 450 MHz, program 449 decimal.
       For CD clock 540 MHz, program 539 decimal.
       For CD clock 675 MHz, program 674 decimal."
      
      Cc: stable@vger.kernel.org
      Cc: Mika Kahola <mika.kahola@intel.com>
      Fixes: b432e5cf ("drm/i915: BDW clock change support")
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.comReviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
      7f1052a8
    • Ramalingam C's avatar
      drm/i915/bxt: Adjusting the error in horizontal timings retrieval · 042ab0c3
      Ramalingam C authored
      In BXT DSI there is no regs programmed with few horizontal timings
      in Pixels but txbyteclkhs.. So retrieval process adds some
      ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
      
      Actually here for the given adjusted_mode, we are calculating the
      value programmed to the port and then back to the horizontal timing
      param in pixels. This is the expected value at the end of get_config,
      including roundup errors. And if that is same as retrieved value
      from port, then retrieved (HW state) adjusted_mode's horizontal
      timings are corrected to match with SW state to nullify the errors.
      Signed-off-by: default avatarRamalingam C <ramalingam.c@intel.com>
      Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      Acked-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1461053894-5058-2-git-send-email-ramalingam.c@intel.com
      042ab0c3
    • Ramalingam C's avatar
      drm/i915/BXT: Retrieving the horizontal timing for DSI · cefc4e18
      Ramalingam C authored
      Retriving the horizontal timings from the port registers as part of
      get_config().
      
      This fixes a division by zero:
      
      [   56.916557] divide error: 0000 [#1] PREEMPT SMP
      [   56.921741] Modules linked in: i915(+) drm_kms_helper syscopyarea
      sysfillrect sysimgblt fb_sys_fops drm intel_gtt agpgart cf
      g80211 rfkill binfmt_misc ax88179_178a kvm_intel kvm irqbypass crc32c_intel
      efivars tpm_tis tpm fuse
      [   56.944106] CPU: 3 PID: 1097 Comm: modprobe Not tainted 4.6.0-rc4+ #433
      [   56.951501] Hardware name: Intel Corp. Broxton M/RVP, BIOS
      BXT1RVPA.X64.0131.B30.1604142217 04/14/2016
      [   56.961908] task: ffff88007a854d00 ti: ffff88007aea0000 task.ti:
      ffff88007aea0000
      [   56.970273] RIP: 0010:[<ffffffffa01235b2>]  [<ffffffffa01235b2>]
      drm_mode_hsync+0x22/0x40 [drm]
      [   56.980043] RSP: 0018:ffff88007aea3788  EFLAGS: 00010206
      [   56.985982] RAX: 000000000788b600 RBX: ffff880073c22108 RCX:
      0000000000000000
      [   56.993957] RDX: 0000000000000000 RSI: ffff88007ab06800 RDI:
      ffff880073c22108
      [   57.001935] RBP: ffff88007aea3788 R08: 0000000000000001 R09:
      ffff880073c221e8
      [   57.009903] R10: ffff880073c22108 R11: 0000000000000001 R12:
      ffff88007a300000
      [   57.017872] R13: ffff880073c22000 R14: ffff880175f78000 R15:
      ffff880175f78798
      [   57.025849] FS:  00007f105d3e6700(0000) GS:ffff88017fd80000(0000)
      knlGS:0000000000000000
      [   57.034894] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      [   57.041317] CR2: 00007f4d485101d0 CR3: 000000007a820000 CR4:
      00000000003406e0
      [   57.049292] Stack:
      [   57.051539]  ffff88007aea37a0 ffffffffa043b632 ffff880175f787c8
      ffff88007aea3810
      [   57.059825]  ffffffffa043d59e ffff880175f787b0 ffff88007ab68c00
      ffff88007aea37f0
      [   57.068128]  ffff880073c221e8 ffff880073c22108 ffff880175f78780
      ffff880100000000
      [   57.076430] Call Trace:
      [   57.079254]  [<ffffffffa043b632>] intel_mode_from_pipe_config+0x82/0xb0
      [i915]
      [   57.087405]  [<ffffffffa043d59e>] intel_modeset_setup_hw_state+0x55e/0xd60
      [i915]
      [   57.095847]  [<ffffffffa043ff94>] intel_modeset_init+0x8e4/0x1630 [i915]
      [   57.103415]  [<ffffffffa047bcf0>] i915_driver_load+0xbe0/0x1980 [i915]
      [   57.110745]  [<ffffffffa0116c19>] drm_dev_register+0xa9/0xc0 [drm]
      [   57.117681]  [<ffffffffa011921d>] drm_get_pci_dev+0x8d/0x1e0 [drm]
      [   57.124600]  [<ffffffff8195f942>] ? _raw_spin_unlock_irqrestore+0x42/0x70
      [   57.132253]  [<ffffffffa03b0384>] i915_pci_probe+0x34/0x50 [i915]
      [   57.139070]  [<ffffffff8149c375>] local_pci_probe+0x45/0xa0
      [   57.145303]  [<ffffffff8149d300>] ? pci_match_device+0xe0/0x110
      [   57.151924]  [<ffffffff8149d6cb>] pci_device_probe+0xdb/0x130
      [   57.158355]  [<ffffffff81579b93>] driver_probe_device+0x223/0x440
      [   57.165169]  [<ffffffff81579e85>] __driver_attach+0xd5/0x100
      [   57.171500]  [<ffffffff81579db0>] ? driver_probe_device+0x440/0x440
      [   57.178510]  [<ffffffff81577736>] bus_for_each_dev+0x66/0xa0
      [   57.184841]  [<ffffffff815793de>] driver_attach+0x1e/0x20
      [   57.190881]  [<ffffffff81578d6e>] bus_add_driver+0x1ee/0x280
      [   57.197212]  [<ffffffff8157abc0>] driver_register+0x60/0xe0
      [   57.203447]  [<ffffffff8149bc50>] __pci_register_driver+0x60/0x70
      [   57.210285]  [<ffffffffa0119450>] drm_pci_init+0xe0/0x110 [drm]
      [   57.216911]  [<ffffffff810dcd8d>] ? trace_hardirqs_on+0xd/0x10
      [   57.223434]  [<ffffffffa023a000>] ? 0xffffffffa023a000
      [   57.229237]  [<ffffffffa023a092>] i915_init+0x92/0x99 [i915]
      [   57.235570]  [<ffffffff810003db>] do_one_initcall+0xab/0x1d0
      [   57.241900]  [<ffffffff810f9eef>] ? rcu_read_lock_sched_held+0x7f/0x90
      [   57.249205]  [<ffffffff81204f18>] ? kmem_cache_alloc_trace+0x248/0x2b0
      [   57.256509]  [<ffffffff811a5eee>] ? do_init_module+0x27/0x1d9
      [   57.262934]  [<ffffffff811a5f26>] do_init_module+0x5f/0x1d9
      [   57.269167]  [<ffffffff8112392f>] load_module+0x20ef/0x27b0
      [   57.275401]  [<ffffffff8111f8e0>] ? store_uevent+0x40/0x40
      [   57.281541]  [<ffffffff81124243>] SYSC_finit_module+0xc3/0xf0
      [   57.287969]  [<ffffffff8112428e>] SyS_finit_module+0xe/0x10
      [   57.294203]  [<ffffffff81960069>] entry_SYSCALL_64_fastpath+0x1c/0xac
      [   57.301406] Code: ff 5d c3 66 0f 1f 44 00 00 0f 1f 44 00 00 8b 87 d8 00 00
      00 55 48 89 e5 85 c0 75 22 8b 4f 68 85 c9 78 1b 69 47 58 e8 03 00 00 99 <f7> f9
      b9 d3 4d 62 10 05 f4 01 00 00 f7 e1 89 d0 c1 e8 06 5d c3
      [   57.322964] RIP  [<ffffffffa01235b2>] drm_mode_hsync+0x22/0x40 [drm]
      [   57.330103]  RSP <ffff88007aea3788>
      [   57.334276] ---[ end trace d414224cb2e2a4cf ]---
      [   57.339861] modprobe (1097) used greatest stack depth: 12048 bytes left
      
      Fixes: 6f0e7535 ("drm/i915/BXT: Get pipe conf from the port registers")
      Signed-off-by: default avatarRamalingam C <ramalingam.c@intel.com>
      Acked-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1461053894-5058-1-git-send-email-ramalingam.c@intel.com
      cefc4e18
    • Chris Wilson's avatar
      drm/i915: Unify GPU resets upon shutdown · e7ae86ba
      Chris Wilson authored
      Both execlists and legacy need to reset the context (and mode) of the
      GPU before we lose control of the system. By resetting the GPU, we
      revert back to default settings. This simplifies the life of any
      subsequent driver (in particular for virtualized setups) as it does not
      then have to try and recover from an unknown condition. As both paths
      need to reset for the same reason, move the reset to a common point.
      
      This unifies the resets added in a647828a (drm/i915: Also perform gpu
      reset under execlist mode) and 8e96d9c4 (drm/i915: reset the GPU on
      context fini).
      
      v2: Restrict the reset to "modern" gen (where we enable HW contexts) to
      try and avoid leaving the machine in an unusable state with a risky
      reset on older GPU. This should keep the status quo as to who performs
      resets (i.e. currently only GPUs with HW contexts perform a reset on
      shutdown).
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Cc: "Niu, Bing" <bing.niu@intel.com>
      Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1461833819-3991-25-git-send-email-chris@chris-wilson.co.uk
      e7ae86ba