- 26 Sep, 2017 40 commits
-
-
Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
-
Bhawanpreet Lakha authored
-Flattening core_dc to dc Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
-
Dmytro Laktyushkin authored
Signed-off-by:
-
Charlene Liu authored
also pass-in correct dispclk tor DMCU Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
-
Bhawanpreet Lakha authored
-Change dcn_ip into pointer -Change dcn_soc into pointer This is needed for flattening of core_dc into dc, as without this the diags build fails Signed-off-by:
-
Corbin McElhanney authored
This comment explains a previous change that adds some complexity to the context free in dc: commit 9ad58779a895 ("drm/amd/display: Fix accessing freed memory") Signed-off-by:Corbin McElhanney <corbin.mcelhanney@amd.com> Reviewed-by:
-
Bhawanpreet Lakha authored
-Change bw_calcs_dceip into pointer -Change bw_calcs_vbios into pointer This is needed for flattening of core_dc into dc, as without this the diags build fails Signed-off-by:
-
Duke Du authored
Signed-off-by:
Duke Du <Duke.Du@amd.com> Reviewed-by:
-
Jerry Zuo authored
Current ref_count inc/dec is not guarded by locks which leads to a raced condition where two threads try to access the variable at the same time. In this case, both might act on the same cached value and inc/dec from the same value, rather than inc/dec by 2. Signed-off-by:
Jerry Zuo <Jerry.Zuo@amd.com> Reviewed-by:
-
Roman Li authored
Added missing reg shift/masks to soc base Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
-
Alex Deucher authored
Until I've had time to test it better. bug: https://bugs.freedesktop.org/show_bug.cgi?id=102372Reviewed-by:
-
Harry Wentland authored
Signed-off-by:
Jordan Lazare <jordan.lazare@amd.com> Signed-off-by:
-
Alex Deucher authored
Enable DC for DCE8 APUs. Signed-off-by:
-
Alex Deucher authored
Add the appropriate resources for APUs: KV: 4 pipes, 7 dig, 3 PPLLs KB/ML: 2 pipes, 6 dig, 2 PPLLs v2: rebase changes Signed-off-by:
-
Alex Deucher authored
DCE 8.1 = Kaveri DCE 8.3 = Kabini/Mullins Signed-off-by:
-
Alex Deucher authored
KV has 7 possible DIG blocks. Signed-off-by:
-
Alex Deucher authored
Signed-off-by:
-
Alex Deucher authored
Add DCE8 APUs to display manager. v2: rebase changes Signed-off-by:
-
Alex Deucher authored
Only used in dce120_resource.c. Signed-off-by:
-
Alex Deucher authored
Not used outside of the dce110_resource.c. v2: make a bunch of other functions static as well. Signed-off-by:
-
Harry Wentland authored
Signed-off-by:
-
Harry Wentland authored
This was broken by "implement DXGI Gamma Ramps" Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Acked-by:
-
Harry Wentland authored
Caused by "add programming for 0 plane case" which was tested on DCN but not on DCE. Signed-off-by:
-
Corbin McElhanney authored
(FF-158) -[FF N-1] HDMI Deep Color Mode incorrect bit depth: FMT_DYNAMIC_EXP_EN is being reset to 0 Signed-off-by:
-
Tony Cheng authored
Signed-off-by:
-
Yongqiang Sun authored
Signed-off-by:
-
Corbin McElhanney authored
Signed-off-by:
-
Harry Wentland authored
Signed-off-by:
-
Harry Wentland authored
Signed-off-by:
-
Tony Cheng authored
40s time out is not sensible. also make all udelay poll happen more frequently since CPU is busy anyways Signed-off-by:
-
Corbin McElhanney authored
Signed-off-by:
-
Yongqiang Sun authored
Signed-off-by:
-
Eric Yang authored
Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
-
Wenjing Liu authored
DP link layer test 400.1.1 fails intermittently. The test device will pull hpd low immediately after verify link cap. Driver reads edid when hpd low that causes the test to fail. Move read edid before verify link cap, so driver will read edid before starting link training Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
-
Anthony Koo authored
Support for gamma correction ramp in Floating Point format Signed-off-by:
-
Corbin McElhanney authored
Signed-off-by:
-
Tony Cheng authored
as well as convert output in ref_cycle to nano sec Signed-off-by:
Logatharshan Thothiralingam <Logatharshan.Thothiralingam@amd.com> Acked-by:
-
Tony Cheng authored
Signed-off-by:
-
Charlene Liu authored
Signed-off-by:
-
