- 17 Jan, 2014 33 commits
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Tero Kristo authored
Clock nodes shall use the services provided by underlying drivers to access the hardware registers instead of direct memory read/write. Thus, change all the code to use the new omap2_clk_readl / omap2_clk_writel APIs for this. Signed-off-by:
Tero Kristo <t-kristo@ti.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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Tero Kristo authored
Using indexed memmaps is required for isolating the actual memory access from the clock code. Now, the driver providing the support for the clock IP block provides the low level routines for reading/writing clock registers also. Signed-off-by:
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Tero Kristo authored
This patch creates a unique node for each clock in the AM43xx power, reset and clock manager (PRCM). Signed-off-by:
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Tero Kristo authored
AM35xx now uses the clock data from device tree. Most of the data is shared with OMAP3xxx, but as there is some delta, a new base .dtsi file is also created for the SoC. Signed-off-by:
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Tero Kristo authored
This patch creates a unique node for each clock in the OMAP3 power, reset and clock manager (PRCM). Signed-off-by:
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Tero Kristo authored
This patch creates a unique node for each clock in the AM33xx power, reset and clock manager (PRCM). Signed-off-by:
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J Keerthy authored
This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk which are used by PCIe phy. It also adds a mux clock to choose the source of optfclk_pciephy_div_clk clock. Signed-off-by:
J Keerthy <j-keerthy@ti.com> Signed-off-by:
Nishanth Menon <nm@ti.com> Acked-by:
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J Keerthy authored
This patch changes apll_pcie_m2_ck to fixed factor clock as there are no configurable divider associated to m2. Signed-off-by:
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J Keerthy authored
The patch adds a mux node to choose the parent of apll_pcie_ck node. Signed-off-by:
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Tero Kristo authored
This patch creates a unique node for each clock in the DRA7 power, reset and clock manager (PRCM). TODO: apll_pcie clock node is still a dummy in this version, and proper support for the APLL should be added. Signed-off-by:
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Tero Kristo authored
This patch creates a unique node for each clock in the OMAP5 power, reset and clock manager (PRCM). Signed-off-by:
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Tero Kristo authored
This patch creates a unique node for each clock in the OMAP4 power, reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly different clock tree which is taken into account in the data. Signed-off-by:
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Tero Kristo authored
clk-43xx.c now contains the clock init functionality for am43xx, including DT clock registration and adding of static clkdev entries. Signed-off-by:
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Tero Kristo authored
clk-3xxx.c now contains the clock init functionality for omap3, including DT clock registration and adding of static clkdev entries. Signed-off-by:
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Tero Kristo authored
OMAP3 has interface clocks in addition to functional clocks, which require special handling for the autoidle and idle status register offsets mainly. Signed-off-by:
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Tero Kristo authored
clk-33xx.c now contains the clock init functionality for am33xx, including DT clock registration and adding of static clkdev entries. This patch also moves the omap2_clk_enable_init_clocks declaration to the driver include, as this is needed by the am33xx clock init code. Signed-off-by:
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Tero Kristo authored
clk-7xx.c now contains the clock init functionality for dra7, including DT clock registration and adding of static clkdev entries. Signed-off-by:
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J Keerthy authored
The patch adds support for DRA7 PCIe APLL. The APLL sources the optional functional clocks for PCIe module. APLL stands for Analog PLL. This is different when comapred with DPLL meaning Digital PLL, the phase detection is done using an analog circuit. Signed-off-by:
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Roger Quadros authored
USB_DPLL must be initialized and locked at boot so that USB modules can work. Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
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Tero Kristo authored
clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by:
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Tero Kristo authored
clk-44xx.c now contains the clock init functionality for omap4, including DT clock registration and adding of static clkdev entries. Signed-off-by:
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Tero Kristo authored
ti,mux-clock provides now a binding for basic mux support. This is just using the basic clock type. Signed-off-by:
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Tero Kristo authored
Some OMAP clocks require knowledge about their parent clockdomain for book keeping purposes. This patch creates a new DT binding for TI clockdomains, which act as a collection of device clocks. Clockdomain itself is rather misleading name for the hardware functionality, as at least on OMAP4 / OMAP5 / DRA7 the clockdomains can be collections of either clocks and/or IP blocks, thus idle-domain or such might be more appropriate. For most cases on these SoCs, the kernel doesn't even need the information and the mappings can be ignored. Signed-off-by:
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Tero Kristo authored
This patch adds support for TI specific gate clocks. These behave as basic gate-clock, but have different ops / hw-ops for controlling the actual gate, for example waiting until the clock is ready. Several sub-types are supported: - ti,gate-clock: basic gate clock with default ops/hwops - ti,clkdm-gate-clock: clockdomain level gate control - ti,dss-gate-clock: gate clock with DSS specific hardware handling - ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling - ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling Signed-off-by:
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Tero Kristo authored
This behaves exactly in similar manner to basic fixed-factor-clock, but adds a few properties on top for handling clock hardware autoidling. Signed-off-by:
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Tero Kristo authored
This patch adds support for TI divider clock binding, which simply uses the basic clock divider to provide the features needed. Signed-off-by:
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Tero Kristo authored
This is a multipurpose clock node, which contains support for multiple sub-clocks. Uses basic composite clock type to implement the actual functionality, and TI specific gate, mux and divider clocks. Signed-off-by:
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Tero Kristo authored
TI clk driver now routes some of the basic clocks through own registration routine to allow autoidle support. This routine just checks a couple of device node properties and adds autoidle support if required, and just passes the registration forward to basic clocks. Signed-off-by:
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Tero Kristo authored
The OMAP clock driver now supports DPLL clock type. This patch also adds support for DT DPLL nodes. Signed-off-by:
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Tero Kristo authored
ti_dt_clk_init_provider() can now be used to initialize the contents of a single clock IP block. This parses all the clocks under the IP block and calls the corresponding init function for them. This patch also introduces a helper function for the TI clock drivers to get register info from DT and append the master IP info to this. Signed-off-by:
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Tero Kristo authored
Some devices require their clocks to be available with a specific dev-id con-id mapping. With DT, the clocks can be found by default only with their name, or alternatively through the device node of the consumer. With drivers, that don't support DT fully yet, add mechanism to register specific clock names. Signed-off-by:
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Tero Kristo authored
SOC_DRA7XX was under wrong menu within Kconfig file, which prevented DRA7XX only build. Fixed the kconfig options for this SoC as we are there. voltage.c needs to be added to the DRA7XX build also, otherwise DRA7XX only build will fail. Signed-off-by:
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Tero Kristo authored
DRA7XX and AM43XX were missing common clock code from the Makefile, which causes build breakage in DRA7XX / AM43XX only builds once clock support for these SoCs is added. Add the missing entries to the Makefile as preparation of this. Signed-off-by:
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- 16 Jan, 2014 7 commits
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Mike Turquette authored
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Stephen Boyd authored
Document the multimedia clock controller found on Qualcomm devices Cc: <devicetree@vger.kernel.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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Stephen Boyd authored
Document the global clock controller found on Qualcomm devices. Cc: <devicetree@vger.kernel.org> Signed-off-by:
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Stephen Boyd authored
Add a driver for the global clock controller found on MSM8660 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Add a driver for the global clock controller found on MSM 8974 based platforms. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Add a driver for the global clock controller found on MSM 8974 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Add a driver for the multimedia clock controller found on MSM 8960 based platforms. This should allow multimedia device drivers to probe and control their clocks. Signed-off-by:
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