- 23 Apr, 2020 1 commit
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Yintian Tao authored
According to the current kiq read register method, there will be race condition when using KIQ to read register if multiple clients want to read at same time just like the expample below: 1. client-A start to read REG-0 throguh KIQ 2. client-A poll the seqno-0 3. client-B start to read REG-1 through KIQ 4. client-B poll the seqno-1 5. the kiq complete these two read operation 6. client-A to read the register at the wb buffer and get REG-1 value Therefore, use amdgpu_device_wb_get() to request reg_val_offs for each kiq read register. v2: fix the error remove v3: fix the print typo v4: remove unused variables Signed-off-by:
Yintian Tao <yttao@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 22 Apr, 2020 39 commits
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Christian König authored
In pp_one_vf mode avoid the extra overhead and read/write the registers without the KIQ. Signed-off-by:
Monk Liu <monk.liu@amd.com> Acked-by:
Yintian Tao <yintian.tao@amd.com> Signed-off-by:
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Dennis Li authored
If set error query ready in amdgpu_ras_late_init, which will cause some IP blocks aren't initialized, but their error query is ready. Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Evan Quan authored
Make code more readable. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Evan Quan authored
This is basically just some code cosmetic. The current design for XGMI setup gput reset is to operate on current device(adev) first and then on other devices from the hive(by another 'for' loop). But actually we can do some sort to the device list(to put current device 1st position) and handle all the devices in a single 'for' loop. V2: added missing hive->hive_lock protection Signed-off-by:
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Evan Quan authored
As for XGMI setup, it should be performed on other devices from the hive also. Signed-off-by:
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Evan Quan authored
As for XGMI setup, it needs to be performed on all the devices from the same hive. Signed-off-by:
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Bernard Zhao authored
Make the code a bit more readable by using a common error handling pattern. Signed-off-by:
Bernard Zhao <bernard@vivo.com> Reviewed-by: Christian König <christian.koenig@amd.com>. Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Kevin Wang authored
clean up unused variable: 1. ring_lru_list 2. ring_lru_list_lock related-commit: drm/amdgpu: remove ring lru handling Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Dennis Li authored
Prefix RAS message printing in gfx/mmhub with PCI device info, which assists the debug in multiple GPU case. Reviewed-by:
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Jiansong Chen authored
Under onevf mode the smu support to other chips is not well verified yet. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
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Jiawei authored
disble vblank in dce_vitual_crtc_commit(), which is skipped under sriov before Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
Jiawei <Jiawei.Gu@amd.com> Signed-off-by:
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Yong Zhao authored
This is convenient for multiple teams to obtain the information. Also, add device info by using dev_info(). Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Reviewed-by:
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Prike Liang authored
Update the smu12_driver_if.h header to follow the pmfw release. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Yuxian Dai authored
for different ASIC support different the number of DPM levels, we should avoid to show the invalid level value. v1 -> v2: follow the suggestion,clarifiy the description for this change Reviewed-by:
Yuxian Dai <Yuxian.Dai@amd.com> Signed-off-by:
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Yong Zhao authored
Turn off the printing by default because it is not very useful, while adding more details. Signed-off-by:
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Yong Zhao authored
Delete two printings which are not very useful, and change one from pr_info() to pr_debug(). Signed-off-by:
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Anthony Koo authored
[Why] there's a bug in the new logic for panel power control. the check is wrong, and will skip panel power control under the wrong conditions. [How] fix to check for NULL panel_cntl Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Wyatt Wood authored
[Why] Current code does not guarantee the correct endianness of memory being copied to fw, specifically in the case where cpu isn't little endian. [How] Windows and Diags are always little endian, so we define a macro that does nothing. Linux already defines this macro and will do the correct endianness conversion. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Rodrigo Siqueira authored
[why] We have seen a green screen after resume from suspend in a Raven system connected with two displays (HDMI and DP) on X based system. We noticed that this issue is related to bad DCC metadata from user space which may generate hangs and consequently an underflow on HUBP. After taking a deep look at the code path we realized that after resume we try to restore the commit with the DCC enabled framebuffer but the framebuffer is no longer valid. [how] This problem was only reported on Raven based system and after suspend, for this reason, this commit adds a new parameter on fill_plane_dcc_attributes() to give the option of disabling DCC programmatically. In summary, for disabling DCC we first verify if is a Raven system and if it is in suspend; if both conditions are true we disable DCC temporarily, otherwise, it is enabled. Co-developed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Stylon Wang authored
[Why] Commit cdde482c is causing regression from changing the order of call sequence. [How] Keep the call sequence and take in extra dm state only if plane-level color management is enabled. Fixes: cdde482c ("drm/amd/display: Refactor color management to take dm plane state") Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
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Yongqiang Sun authored
[Why] Since ABM resource is mapped to stream res, all the ABM access should via stream res. [How] Get ABM instance from stream res instead of resource pool. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Xiaodong Yan authored
[Why] When link loss happened, monitor can not light up if only re-train the link. [How] Blank all the DP streams on this link before re-train the link, and then unblank the stream Signed-off-by:
Xiaodong Yan <Xiaodong.Yan@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[why] Organizational Unit Identifier register is optional, and its presence is published via Down Stream Port Count register. Writing this register when not available will result in errors [how] Read this register and continue writing OUI only if the panel has the support advertised. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Anthony Koo authored
[Why] it doesn't represent panel specifically, it's more like the control logic for the panel [How] change from panel to panel cntl to make it a bit more clear Signed-off-by:
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Jaehyun Chung authored
[Why] HW rotation was enabled in DAL3 but hubp cursor calculations for HW roation were only added to dcn20. [How] Add hubp cursor position calculation changes to dcn10. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] We expect to be able to perform immediate flipping without having to recalculate and update all the watermarks. There are certain usecases today (1080p @ 90deg, 2160p @ 90deg) such that we get a urgency value of 0 for frac_urg_bw_flip because we're explicitly passing in a value of "false" for requiring immediate flip support into the DLG calculation. [How] Always pass in true into the calculation. With this we get a correct non-zero value for frac_urg_bw_flip. Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Dmytro Laktyushkin authored
This prevents dpcd access on virtual links. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Anthony Koo authored
[Why] without destroy it is causing a memory leak [How] destroy panel on link destruct Signed-off-by:
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Paul Hsieh authored
[Why] Driver already get display clock from SMU base on MHz, but driver read again and mutiple 1000 cause wait loop value is overflow. [How] remove coding error Signed-off-by:
Paul Hsieh <paul.hsieh@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Anthony Koo authored
[Why] panel power sequencer is currently just sitting in hwseq but it really it tied to internal panels [How] make a new panel struct to contain power sequencer code Signed-off-by:
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Anthony Koo authored
[Why] Backlight adjustment is tied to a specific display. So make the calls target a link rather than making it a global state. [How] make all backlight calls link based Signed-off-by:
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Sung Lee authored
[WHY] In certain conditions with low pixel clock, some values in DML may go past the max due to margining for latency hiding. This causes assertions to get hit. [HOW] If the pixel clock is low and some values are high, cap it to the max. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] - Driver does not recognize new definitions of psr states. - Internal tool is required for checking if psr is active. [How] - Parse psr state correctly so that driver will recognize psr state. - Add visual confirmation that psr is active using existing mechanisms. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
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Aric Cyr authored
Don't skip MPCC tree updates if requested. Signed-off-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
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Aric Cyr authored
Some cases were incorrectly reporting the wrong visual confirm, even though they were working as expected. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] Color blending for NV12 formats is incorrect because we're using the predefined SRGB degamma. [How] Calculate the correct input transfer function for degamma from the color module depending on what the actual surface format is. Signed-off-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
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Haiyi Zhou authored
[Why] Certain displays may experience blanking if infopacket max range does not equal nominal refresh rate. [How] Add additional infopacket versions to program range to full or forced range in freesync states. This does not change the vrr logic. Signed-off-by:
Haiyi Zhou <haiyi.zhou@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] On ASIC without ABM support (most dGPU) we run into a null pointer dereference when attempting to set the backlight level. [How] This function requires ABM, so fix up the condition to only allow DMCU to be optional. Signed-off-by:
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