- 07 Jul, 2015 1 commit
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Pankaj Dev authored
Incorrect register offset used for sthi407 clockgenC Signed-off-by:
Pankaj Dev <pankaj.dev@st.com> Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@linaro.org> Fixes: 51306d56 ("clk: st: STiH407: Support for clockgenC0") Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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- 06 Jul, 2015 7 commits
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Sascha Hauer authored
On the MT8173 the clocks are provided by different units. To enable the critical clocks we must be sure that all parent clocks are already registered, otherwise the parents of the critical clocks end up being unused and get disabled later. To find a place where all parents are registered we try each time after we've registered some clocks if all known providers are present now and only then we enable the critical clocks Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
James Liao <jamesjj.liao@mediatek.com> [sboyd@codeaurora.org: Marked function and data __init] Signed-off-by:
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Gabriel Fernandez authored
This patch fixes the mux bit-setting for ClockgenA9. Signed-off-by:
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Pankaj Dev authored
Add the CLK_GET_RATE_NOCACHE flag to all the clocks with recalc ops, so that they reflect Hw rate after CPS wake-up when a clk_get_rate() is called Signed-off-by:
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Giuseppe Cavallaro authored
While proving lock, the following warning happens and it is fixed after initializing lock in the setup function INFO: trying to register non-static key. the code is fine but needs lockdep annotation. turning off the locking correctness validator. CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.27-02861-g39df285-dirty #33 [<c00154ac>] (unwind_backtrace+0x0/0xf4) from [<c0011b50>] (show_stack+0x10/0x14) [<c0011b50>] (show_stack+0x10/0x14) from [<c00689ac>] (__lock_acquire+0x900/0xb14) [<c00689ac>] (__lock_acquire+0x900/0xb14) from [<c0069394>] (lock_acquire+0x68/0x7c) [<c0069394>] (lock_acquire+0x68/0x7c) from [<c04958f8>] (_raw_spin_lock_irqsave+0x48/0x5c) [<c04958f8>] (_raw_spin_lock_irqsave+0x48/0x5c) from [<c0381e6c>] (clk_gate_endisable+0x28/0x88) [<c0381e6c>] (clk_gate_endisable+0x28/0x88) from [<c0381ee0>] (clk_gate_enable+0xc/0x14) [<c0381ee0>] (clk_gate_enable+0xc/0x14) from [<c0386c68>] (flexgen_enable+0x28/0x40) [<c0386c68>] (flexgen_enable+0x28/0x40) from [<c037f260>] (__clk_enable+0x5c/0x9c) [<c037f260>] (__clk_enable+0x5c/0x9c) from [<c037f558>] (clk_enable+0x18/0x2c) [<c037f558>] (clk_enable+0x18/0x2c) from [<c064a1dc>] (st_lpc_of_register+0xc0/0x248) [<c064a1dc>] (st_lpc_of_register+0xc0/0x248) from [<c0649e44>] (clocksource_of_init+0x34/0x58) [<c0649e44>] (clocksource_of_init+0x34/0x58) from [<c0637ddc>] (sti_timer_init+0x10/0x18) [<c0637ddc>] (sti_timer_init+0x10/0x18) from [<c06343f8>] (time_init+0x20/0x30) [<c06343f8>] (time_init+0x20/0x30) from [<c0632984>] (start_kernel+0x20c/0x2e8) [<c0632984>] (start_kernel+0x20c/0x2e8) from [<40008074>] (0x40008074) Signed-off-by:
Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by:
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Gabriel Fernandez authored
This patch fixes the value for disabling the FSYN channel clock. The 'is_enabled' returned value is also fixed. Signed-off-by:
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Gabriel Fernandez authored
Remove this duplicated code due to a bad copy / paste. Signed-off-by:
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Hai Li authored
Since the parent rate has been recalculated, pixel RCG clock should rely on it to find the correct M/N values during set_rate, instead of calling __clk_round_rate() to its parent again. Signed-off-by:
Hai Li <hali@codeaurora.org> Tested-by:
Archit Taneja <architt@codeaurora.org> Fixes: 99cbd064 ("clk: qcom: Support display RCG clocks") [sboyd@codeaurora.org: Silenced unused parent variable warning] Signed-off-by:
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- 02 Jul, 2015 4 commits
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David Dueck authored
Do not leak memory and free irqs in case of an error. Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
David Dueck <davidcdueck@googlemail.com> Signed-off-by:
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Daniel Thompson authored
If stm32f4_rcc_lookup() is called with primary == 0 and secondary == 192 then it will read beyond the end of the table array due to an out-by-one error in the range check. In addition to the fixing the inequality we also modify the r.h.s. to make it even more explicit that we are comparing against the size of table in bits. Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Daniel Thompson <daniel.thompson@linaro.org> Acked-by:
Maxime Coquelin <mcoquelin.stm32@gmail.com> Fixes: 358bdf89 ("clk: stm32: Add clock driver for STM32F4[23]xxx devices") Signed-off-by:
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Ray Jui authored
A 32-bit variable should be type casted to 64-bit before arithmetic operation and assigning it to a 64-bit variable Reported-by:
Ray Jui <rjui@broadcom.com> Fixes: 5fe225c1 ("clk: iproc: add initial common clock support") Signed-off-by:
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Ray Jui authored
of_property_read_string_index takes array of pointers and assign them to strings read from device tree property. No additional memory allocation is needed prior to calling of_property_read_string_index. In fact, since the array of pointers will be re-assigned to other strings, any memory that it points to prior to calling of_property_read_string_index will be leaked Reported-by:
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- 22 Jun, 2015 2 commits
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Daniel Thompson authored
The driver supports decoding and statically modelling PLL state (i.e. we inherit state from bootloader) and provides support for all peripherals that support simple one-bit gated clocks. The covers all peripherals whose clocks come from the AHB, APB1 or APB2 buses. It has been tested on an STM32F429I-Discovery board. The clock counts for TIM2, USART1 and SYSTICK are all set correctly and the wall clock looks OK when checked with a stopwatch. I have also tested a prototype driver for the RNG hardware. The RNG clock is correctly enabled by the framework (also did inverse test and proved that by changing DT to configure the wrong clock bit then we observe the RNG driver to fail). Signed-off-by:
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Daniel Thompson authored
This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block. Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by:
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- 20 Jun, 2015 7 commits
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Michael Turquette authored
Merge tag 'tegra-for-4.2-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.2-rc1 This contains the EMC clock driver that's been exhaustively reviewed and tested. It also includes a change to the clock core that allows a clock provider to perform low-level reparenting of clocks. This is required by the EMC clock driver because the reparenting needs to be done at a very specific point in time during the EMC frequency switch.
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Michael Turquette authored
Folded into this merge commit is a build error fix: s/clk/core in clk_change_rate due to the new struct clk_core
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Thomas Abraham authored
Exynos4210 based platforms have switched over to use generic cpufreq driver for cpufreq functionality. So the Exynos specific cpufreq support for these platforms can be removed. Changes by Bartlomiej: - dropped Exynos5250 support removal for now - updated exynos-cpufreq.[c,h] Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Thomas Abraham <thomas.ab@samsung.com> Signed-off-by:
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by:
Michael Turquette <mturquette@baylibre.com>
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Thomas Abraham authored
The new CPU clock type allows the use of generic CPUfreq driver. Switch Exynos4210 to using generic cpufreq driver. Changes by Bartlomiej: - removed non-Exynos4210 support for now Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by:
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Thomas Abraham authored
With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos4210. Changes by Bartlomiej: - fixed issue with wrong dividers being setup by Common Clock Framework (by an addition of CLK_RECALC_NEW_RATES clock flag to mout_apll clock, without this change cpufreq-dt driver showed ~10 mA larger energy consumption when compared to cpufreq-exynos one when "performance" cpufreq governor was used on Exynos4210 SoC based Origen board), this was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in the original patchset (in "[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update clock flags") but using these flags is not sufficient to fix the issue observed - removed Exynos5250 and Exynos5420 support for now Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by:
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Thomas Abraham authored
The CPU clock provider supplies the clock to the CPU clock domain. The composition and organization of the CPU clock provider could vary among Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers and gates. This patch defines a new clock type for CPU clock provider and adds infrastructure to register the CPU clock providers for Samsung platforms. Changes by Bartlomiej: - fixed issue with setting lower dividers before the parent clock speed was lowered (the issue resulted in lockup on Exynos4210 SoC based Origen board when "ondemand" cpufreq governor was stress tested) - fixed missing spin_unlock on error in exynos_cpuclk_post_rate_change() problem by moving cfg_data search outside of the spin locked area - removed leftover kfree() in exynos_register_cpu_clock() that could result in dereferencing the NULL pointer on error - moved spin_lock earlier in exynos_cpuclk_pre_rate_change() to cover reading of E4210_SRC_CPU and E4210_DIV_CPU1 registers - added missing "last chance" checks to wait_until_divider_stable() and wait_until_mux_stable() (needed in case that IRQ handling took long time to proceed and resulted in function printing incorrect error message about timeout) - moved E4210_CPU_DIV[0,1]() macros just before their only users, this resulted in moving them from patch #2 to patch #3/6 ("clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock") - removed E5250_CPU_DIV[0,1](), E5420_EGL_DIV0() and E5420_KFC_DIV() macros for now - added my Copyrights to drivers/clk/samsung/clk-cpu.c Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: -
Bartlomiej Zolnierkiewicz authored
This flag is needed to fix the issue with wrong dividers being setup by Common Clock Framework when using the new Exynos cpu clock support. The issue happens because clk_core_set_rate_nolock() calls clk_calc_new_rates(clk, rate) before both pre/post clock notifiers have a chance to run. In case of Exynos cpu clock support pre/post clock notifiers are registered for mout_apll clock which is a parent of armclk cpu clock and dividers are modified in both pre and post clock notifier. This results in wrong dividers values being later programmed by clk_change_rate(top). To workaround the problem CLK_RECALC_NEW_RATES flag is added and it is set for mout_apll clock later so the correct divider values are re-calculated after both pre and post clock notifiers had run. For example when using "performance" governor on Exynos4210 Origen board the cpufreq-dt driver requests to change the frequency from 1000MHz to 1200MHz and after the change state of the relevant clocks is following: Without use of CLK_GET_RATE_NOCACHE flag: fout_apll rate: 1200000000 fout_apll_div_2 rate: 600000000 mout_clkout_cpu rate: 600000000 div_clkout_cpu rate: 600000000 clkout_cpu rate: 600000000 mout_apll rate: 1200000000 armclk rate: 1200000000 mout_hpm rate: 1200000000 div_copy rate: 300000000 div_hpm rate: 300000000 mout_core rate: 1200000000 div_core rate: 1200000000 div_core2 rate: 1200000000 arm_clk_div_2 rate: 600000000 div_corem0 rate: 300000000 div_corem1 rate: 150000000 div_periph rate: 300000000 div_atb rate: 300000000 div_pclk_dbg rate: 150000000 sclk_apll rate: 1200000000 sclk_apll_div_2 rate: 600000000 With use of CLK_GET_RATE_NOCACHE flag: fout_apll rate: 1200000000 fout_apll_div_2 rate: 600000000 mout_clkout_cpu rate: 600000000 div_clkout_cpu rate: 600000000 clkout_cpu rate: 600000000 mout_apll rate: 1200000000 armclk rate: 1200000000 mout_hpm rate: 1200000000 div_copy rate: 200000000 div_hpm rate: 200000000 mout_core rate: 1200000000 div_core rate: 1200000000 div_core2 rate: 1200000000 arm_clk_div_2 rate: 600000000 div_corem0 rate: 300000000 div_corem1 rate: 150000000 div_periph rate: 300000000 div_atb rate: 240000000 div_pclk_dbg rate: 120000000 sclk_apll rate: 150000000 sclk_apll_div_2 rate: 75000000 Without this change cpufreq-dt driver showed ~10 mA larger energy consumption when compared to cpufreq-exynos one when "performance" cpufreq governor was used on Exynos4210 SoC based Origen board. This issue was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in the original Exynos cpu clock patchset (in "[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update clock flags" patch) but usage of these flags is not sufficient to fix the issue observed. Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by:
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- 18 Jun, 2015 12 commits
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Joachim Eastwood authored
Add DT binding documentation for lpc1850-ccu clk driver. Signed-off-by:
Joachim Eastwood <manabian@gmail.com> Signed-off-by:
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Joachim Eastwood authored
Add driver for NXP LPC18xx/43xx Clock Control Unit (CCU). The CCU provides fine grained gating of most clocks present in the SoC. Signed-off-by:
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Joachim Eastwood authored
Add DT binding documentation for lpc1850-cgu driver. Signed-off-by:
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Joachim Eastwood authored
Add driver for NXP LPC18xx/43xx Clock Generation Unit (CGU). The CGU contains several clock generators and output stages that route the clocks either directly to peripherals or to a Clock Control Unit (CCU). Signed-off-by:
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Murali Karicheri authored
Main PLL controller has post divider bits in a separate register in pll controller. Use the value from this register instead of fixed divider when available. Signed-off-by:
Murali Karicheri <m-karicheri2@ti.com> Signed-off-by:
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Michael Turquette authored
Merge tag 'sunxi-clocks-for-4.2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner clocks additions for 4.2 One error fix, and one patch to add support for the USB clock found on the Allwinner A23 and A33
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Boris Brezillon authored
The crypto SRAM, used by the armada 370 cpuidle code to workaround a bug in the BootROM code, requires the crypto clk to be up and running. Flag the crypto clk as IGNORE_UNUSED until we add the proper infrastructure to define the crypto SRAM in the DT and reference the crypto clk in this SRAM node. Reported-by:
Kevin Hilman <khilman@linaro.org> Signed-off-by:
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Ray Jui authored
Remove old Cygnus dummy clock binding document, as it's replaced by Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt Signed-off-by:
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Ray Jui authored
The Broadcom Cygnus SoC is architected under the iProc architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, MIPIPLL, all dervied from an onboard crystal. Cygnus also has various ASIU clocks that are derived directly from the onboard crystal. Signed-off-by:
Scott Branden <sbranden@broadcom.com> Signed-off-by:
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Ray Jui authored
The clock code under drivers/clk/bcm now contains code for both the Broadcom mobile SoCs and the iProc SoCs. Change the the makefile dependency to be under config flag CONFIG_ARCH_BCM that's enabled for both families of SoCs Signed-off-by:
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Ray Jui authored
This adds basic and generic support for various iProc PLLs and clocks including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks. SoCs under the iProc architecture can define their specific register offsets and clock parameters for their PLL and clock controllers. These parameters can be passed as arugments into the generic iProc PLL and clock setup functions Derived from code originally provided by Jonathan Richardson <jonathar@broadcom.com> Signed-off-by:
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Ray Jui authored
Document the device tree binding for Broadcom iProc architecture based clock controller Signed-off-by:
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- 17 Jun, 2015 3 commits
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Michael Turquette authored
Signed-off-by: -
Michael Turquette authored
Merge branch 'clk-shmobile-for-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
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Michael Turquette authored
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- 12 Jun, 2015 2 commits
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Dan Carpenter authored
This error handling hopefully isn't needed but it make the static checkers happy. Signed-off-by:
Carlo Caione <carlo@endlessm.com> Signed-off-by:
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Stephen Boyd authored
A recent change to mark parent names as const missed this struct member so we get warnings like: drivers/clk/pxa/clk-pxa25x.c:122:2: warning: initialization discards 'const' qualifier from pointer target type Fix it. Reported-by:
kbuild test robot <fengguang.wu@intel.com> Acked-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
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- 10 Jun, 2015 2 commits
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Maxime Coquelin authored
The debug_node field is only used when DEBUG_FS config is selected, so declare it only if DEBUG_FS is selected. Signed-off-by:
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Daniel Thompson authored
Currently it is not made explicit why clk_fixed_set_rate() can ignore its arguments and unconditionally return success. Add a comment to explain this. We also mark the clk_ops table const since it should never be modified at runtime. Suggested-by:
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