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    • David VomLehn's avatar
      MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs · 010c108d
      David VomLehn authored
      The MIPS processor is limited to 64 external interrupt sources. Using a
      greater number without IRQ sharing requires reading platform-specific
      registers. On such platforms, reading the IntCtl register to determine
      which interrupt corresponds to a timer interrupt will not work.
      
      On MIPSR2 systems there is a solution - the TI bit in the Cause register,
      specifically indicates that a timer interrupt has occured. This patch uses
      that bit to detect interrupts for MIPSR2 processors, which may be expected
      to work regardless of how the timer interrupt may be routed in the hardware.
      
      Signed-off-by: David VomLehn (dvomlehn@cisco.com)
      To: linux-mips@linux-mips.org
      Patchwork: http://patchwork.linux-mips.org/patch/804/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      010c108d