- 26 Aug, 2015 29 commits
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Thomas Gleixner authored
The gpio interrupt handling of octeon contains a homebrewn flow handler which calls either handle_level_irq or handle_edge_irq depending on the trigger type. Thats an extra conditional and call in the interrupt handling path. The proper way to handle different types and therefor different flows is to update the handler in the irq_set_type() callback. Remove the extra indirection and add the handler update to octeon_irq_ciu_gpio_set_type(). At mapping time it defaults to handle_level_irq which gets updated if the device tree contains a different trigger type. Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Cc: David Daney <david.daney@cavium.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/10704/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Thomas Gleixner authored
The various interrupt flow handlers in ath79 are cascading interrupt handlers. They all have a disable_irq_nosync()/enable_irq() pair around the generic_handle_irq() call. The value of this disable/enable is zero because its a complete noop: disable_irq_nosync() merily increments the disable count without actually masking the interrupt. enable_irq() soleley decrements the disable count without touching the interrupt chip. The interrupt cannot arrive again because the complete call chain runs with interrupts disabled. Remove it. Signed-off-by:
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Thomas Gleixner authored
bcsr_csc_handler() is a cascading interrupt handler. It has a disable_irq_nosync()/enable_irq() pair around the generic_handle_irq() call. The value of this disable/enable is zero because its a complete noop: disable_irq_nosync() merily increments the disable count without actually masking the interrupt. enable_irq() soleley decrements the disable count without touching the interrupt chip. The interrupt cannot arrive again because the complete call chain runs with interrupts disabled. Remove it. [ralf@linux-mips.org: Fold in followup fix from Thomas Gleixner.] Signed-off-by:
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Thomas Gleixner authored
Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by:
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Thomas Gleixner authored
Hand in irq_data and avoid the redundant lookup of irq_desc. Originally-from: Jiang Liu <jiang.liu@linux.intel.com> Signed-off-by:
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Jiang Liu authored
This is a preparatory patch for moving irq_data struct members. Signed-off-by:
Jiang Liu <jiang.liu@linux.intel.com> Signed-off-by:
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Thomas Gleixner authored
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by:
Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
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Thomas Gleixner authored
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by:
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Thomas Gleixner authored
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by:
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Thomas Gleixner authored
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by:
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Markos Chandras authored
Set up the I6400 FTLB probability similar to P5600 and proAptiv. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10652/Signed-off-by:
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Markos Chandras authored
R6 has dropped the MMUExtDef field from the config4 register and it now returns 0. However, the return value means nothing in that case and the only supported configuration for R6 is the VTLB+FTLB (MMUextDef == 3). As a result, rework the code so that the correct value is set for R6 cores. Signed-off-by:
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Markos Chandras authored
Add a default case for the FTLB enable/disable code. This will be used to detect that something went wrong in the set_ftlb_enable() function either because that function knows nothing about the running core, or simply because the core can't turn its FTLB on/off. Signed-off-by:
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Markos Chandras authored
We are so early in the boot process where we really don't want to stall and wait for CP0 FTLB related changes become visible so just drop the cp0 hazard barrier. Signed-off-by:
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Markos Chandras authored
CM3 uses a 64-bit counter and compare registers so add support for them in the GIC counter interrupt. Signed-off-by:
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Markos Chandras authored
Previously, the GIC accessors were only accessing u32 registers but newer CMs may actually be 64-bit on MIPS64 cores. As a result of which, extended these accessors to support 64-bit reads and writes. Signed-off-by:
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Markos Chandras authored
The CM cache error reporting code is not Malta specific and as such it should live in the mips-cm.c file. Moreover, CM2 and CM3 differ in the way cache errors are being recorded to the registers so extend the previous code to add support for the CM3 as well. Signed-off-by:
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Markos Chandras authored
The GCR CPC base register is 64-bit on 64-bit processors so use the appropriate field. Signed-off-by:
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Markos Chandras authored
The CMGCRBase register (CP0, 15, 3) register is 64-bit on MIPS64 so we change its type to unsigned long. Signed-off-by:
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Markos Chandras authored
Previously, the CM accessors were only accessing CM registers as u32 types instead of using the native CM register with. However, newer CMs may actually be 64-bit on MIPS64 cores. Fortunately, current 64-bit CMs (CM3) hold all the useful configuration bits in the lower half of the 64-bit registers (at least most of them) so they can still be accessed using the current 32-bit accessors. Signed-off-by:
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Markos Chandras authored
Allow platforms to perform platform-specific steps before configuring the L2 cache. This is necessary for platforms with CM3 since the L2 parameters no longer live in the Config2 register. Signed-off-by:
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Paul Burton authored
Detect the L2 cache configuration from GCR_L2_CONFIG when a CM3 is present in the system, rather than from Config2 which does not expose the L2 configuration on I6400. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Signed-off-by:
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Paul Burton authored
Provide accessor functions for the GCR_L2_CONFIG register introduced with CM3, and define the bits included in the register. Signed-off-by:
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Paul Burton authored
Provide a function to trivially return the version of the CM present in the system, or 0 if no CM is present. The mips_cm_revision() will be used later on to determine the CM register width, so it must not use the regular CM accessors to read the revision register since that will lead to build failures due to recursive inlines. Signed-off-by:
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Markos Chandras authored
R6 does not support the MIPS MT ASE and the CMP/SMP options so restrict them in order to prevent users from selecting incompatible SMP configuration for R6 cores. We also disable the CPS/SMP option because its support hasn't been added to the CPS code yet. Signed-off-by:
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Markos Chandras authored
Add a case in cpu_probe_mips for the MIPS I6400 processor ID, which sets the CPU type to the new CPU_I6400. Signed-off-by:
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Markos Chandras authored
Add a CPU_I6400 case to various switch statements, doing the same thing as for CPU_P5600. Signed-off-by:
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Markos Chandras authored
Add a Processor ID and CPU type for the MIPS I6400 core. Signed-off-by:
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Alban Bedel authored
Remove the ugly cross tree include now that IRQCHIP_DECLARE moved to linux/irqchip.h. Signed-off-by:
Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10633/Signed-off-by:
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- 24 Aug, 2015 2 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsiLinus Torvalds authored
Pull SCSI fixes from James Bottomley: "A couple of major (hang and deadlock) fixes with fortunately fairly rare triggering conditions. The PM oops is only really triggered by people using enclosure services (rare) and the fnic driver is mostly used in enterprise environments" * tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: SCSI: Fix NULL pointer dereference in runtime PM fnic: Use the local variable instead of I/O flag to acquire io_req_lock in fnic_queuecommand() to avoid deadloack
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- 23 Aug, 2015 3 commits
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git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds authored
Pull MIPS bug fixes from Ralf Baechle: "Two more fixes for 4.2. One fixes a build issue with the LLVM assembler - LLVM assembler macro names are case sensitive, GNU as macro names are insensitive; the other corrects a license string (GPL v2, not GPLv2) such that the module loader will recognice the license correctly" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: FIRMWARE: bcm47xx_nvram: Fix module license. MIPS: Fix LLVM build issue.
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git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfsLinus Torvalds authored
Pull 9p regression fix from Al Viro: "Fix for breakage introduced when switching p9_client_{read,write}() to struct iov_iter * (went into 4.1)" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: 9p: ensure err is initialized to 0 in p9_client_read/write -
Vincent Bernat authored
Some use of those functions were providing unitialized values to those functions. Notably, when reading 0 bytes from an empty file on a 9P filesystem, the return code of read() was not 0. Tested with this simple program: #include <assert.h> #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> #include <unistd.h> int main(int argc, const char **argv) { assert(argc == 2); char buffer[256]; int fd = open(argv[1], O_RDONLY|O_NOCTTY); assert(fd >= 0); assert(read(fd, buffer, 0) == 0); return 0; } Cc: stable@vger.kernel.org # v4.1 Signed-off-by:Vincent Bernat <vincent@bernat.im> Signed-off-by:
Al Viro <viro@zeniv.linux.org.uk>
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- 22 Aug, 2015 6 commits
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git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds authored
Pull ARM fixes from Russell King: "Another couple of small ARM fixes. A patch from Masahiro Yamada who noticed that "make -jN all zImage" would end up generating bad images where N > 1, and a patch from Nicolas to fix the Marvell CPU user access optimisation code when page faults are disabled" * 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: ARM: 8418/1: add boot image dependencies to not generate invalid images ARM: 8414/1: __copy_to_user_memcpy: fix mmap semaphore usage
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 fixes from Ingo Molnar: "Various low level fixes: fix more fallout from the FPU rework and the asm entry code rework, plus an MSI rework fix, and an idle-tracing fix" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/fpu/math-emu: Fix crash in fork() x86/fpu/math-emu: Fix math-emu boot crash x86/idle: Restore trace_cpu_idle to mwait_idle() calls x86/irq: Build correct vector mapping for multiple MSI interrupts Revert "sched/x86_64: Don't save flags on context switch"
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull perf fixes from Ingo Molnar: "Tooling fixes: a 'perf record' deadlock fix plus debuggability fixes" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf top: Show backtrace when handling a SIGSEGV on --stdio mode perf tools: Fix buildid processing perf tools: Make fork event processing more resilient perf tools: Avoid deadlock when map_groups are broken
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull irq fixes from Thomas Gleixner: "A series of small fixlets for a regression visible on OMAP devices caused by the conversion of the OMAP interrupt chips to hierarchical interrupt domains. Mostly one liners on the driver side plus a small helper function in the core to avoid open coded mess in the drivers" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/crossbar: Restore set_wake functionality irqchip/crossbar: Restore the mask on suspend behaviour ARM: OMAP: wakeupgen: Restore the irq_set_type() mechanism irqchip/crossbar: Restore the irq_set_type() mechanism genirq: Introduce irq_chip_set_type_parent() helper genirq: Don't return ENOSYS in irq_chip_retrigger_hierarchy
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull timer fixes from Thomas Gleixner: "Two minimalistic fixes for 4.2 regressions: - Eric fixed a thinko in the timer_list base switching code caused by the overhaul of the timer wheel. It can cause a cpu to see the wrong base for a timer while we move the timer around. - Guenter fixed a regression for IMX if booted w/o device tree, where the timer interrupt is not initialized and therefor the machine fails to boot" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource/imx: Fix boot with non-DT systems timer: Write timer->flags atomically -
Ingo Molnar authored
During later stages of math-emu bootup the following crash triggers: math_emulate: 0060:c100d0a8 Kernel panic - not syncing: Math emulation needed in kernel CPU: 0 PID: 1511 Comm: login Not tainted 4.2.0-rc7+ #1012 [...] Call Trace: [<c181d50d>] dump_stack+0x41/0x52 [<c181c918>] panic+0x77/0x189 [<c1003530>] ? math_error+0x140/0x140 [<c164c2d7>] math_emulate+0xba7/0xbd0 [<c100d0a8>] ? fpu__copy+0x138/0x1c0 [<c1109c3c>] ? __alloc_pages_nodemask+0x12c/0x870 [<c136ac20>] ? proc_clear_tty+0x40/0x70 [<c136ac6e>] ? session_clear_tty+0x1e/0x30 [<c1003530>] ? math_error+0x140/0x140 [<c1003575>] do_device_not_available+0x45/0x70 [<c100d0a8>] ? fpu__copy+0x138/0x1c0 [<c18258e6>] error_code+0x5a/0x60 [<c1003530>] ? math_error+0x140/0x140 [<c100d0a8>] ? fpu__copy+0x138/0x1c0 [<c100c205>] arch_dup_task_struct+0x25/0x30 [<c1048cea>] copy_process.part.51+0xea/0x1480 [<c115a8e5>] ? dput+0x175/0x200 [<c136af70>] ? no_tty+0x30/0x30 [<c1157242>] ? do_vfs_ioctl+0x322/0x540 [<c104a21a>] _do_fork+0xca/0x340 [<c1057b06>] ? SyS_rt_sigaction+0x66/0x90 [<c104a557>] SyS_clone+0x27/0x30 [<c1824a80>] sysenter_do_call+0x12/0x12 The reason is the incorrect assumption in fpu_copy(), that FNSAVE can be executed from math-emu kernels as well. Don't try to copy the registers, the soft state will be copied by fork anyway, so the child task inherits the parent task's soft math state. With this fix applied math-emu kernels boot up fine on modern hardware and the 'no387 nofxsr' boot options. Cc: Andy Lutomirski <luto@amacapital.net> Cc: Bobby Powers <bobbypowers@gmail.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Quentin Casasnovas <quentin.casasnovas@oracle.com> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by:Ingo Molnar <mingo@kernel.org>
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