- 06 Apr, 2017 24 commits
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Tom St Denis authored
Use new WREG32_FIELD15 macro Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro Signed-off-by:
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Tom St Denis authored
Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD macro Signed-off-by:
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Tom St Denis authored
It's not used in gfx 6/7/8 so drop it from gfx 9 as well. Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro. Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro. Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro. Signed-off-by:
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Tom St Denis authored
Introduce WREG32_FIELD15 macro for SOC15 architectures. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Xie authored
Signed-off-by:
Alex Xie <AlexBin.Xie@amd.com> Reviewed-by:
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Christian König authored
We need an array of pointers to IRQ sources, not an array of sources. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Tom St Denis authored
Signed-off-by:
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Tom St Denis authored
Had the wrong sense in the loop Signed-off-by:
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Christian König authored
The two hubs are just instances of the same hardware, so the register bits are identical. v2: keep the function pointer Signed-off-by:
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Zhang, Jerry authored
Set reasonable defaults per family. v2: set both of them in gmc v3: move vm size and block size in vm manager v4: squash in warning fix from Alex Xie v5: squash in min() warning fix Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Tom St Denis authored
Signed-off-by:
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Tom St Denis authored
Clean up a toggle with ?:. Signed-off-by:
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Tom St Denis authored
Signed-off-by:
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Tom St Denis authored
Swap read/write pattern for WREG32_FIELD() Signed-off-by:
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Tom St Denis authored
Swap read/write pattern for WREG32_FIELD() Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD_OFFSET() to clean up code. Signed-off-by:
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Alex Deucher authored
Set the ready flag to reflect this. Reviewed-by:
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Christian König authored
The two hubs are just instances of the same hardware, so the register bits are identical. v2: only remove get_vm_protection_bits for now Signed-off-by:
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Christian König authored
This avoids merging them together on page fault. v2: squash in 64-bit division fix Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by:
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- 05 Apr, 2017 14 commits
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Christian König authored
Implement AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS using TTM_PL_FLAG_CONTIGUOUS instead of a placement limit. That allows us to better handle CPU accessible placements. v2: prevent virtual BO start address from overflowing Signed-off-by:
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Christian König authored
We should probably rename amdgpu_gart_funcs sooner or later. Reviewed-by:
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Christian König authored
Remove some of the extra checks where they don't hurt us. Reviewed-by:
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Christian König authored
Abort early if there is nothing todo and correctly indent the "if"s. Reviewed-by:
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Christian König authored
The name is a bit confusing and the extra "? true : false" is superflous. Additional to that remove setting the reset counter directly after checking it. Reviewed-by:
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Christian König authored
Not used any more. Reviewed-by:
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Christian König authored
Try to clean up amdgpu.h. Reviewed-by:
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Christian König authored
Match our defines with what the hw uses. Reviewed-by:
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Christian König authored
We will probably never see this combination. Signed-off-by:
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Christian König authored
This allows drivers to specify if they need a contiguous allocation or not. v2: use space instead of tab Signed-off-by:
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Christian König authored
This allows the driver to handle io_mem mappings on their own. Signed-off-by:
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Christian König authored
No need to implement the same logic twice. Also check if the busy placements are identical to the already scanned placements before checking them. v2: improve check even more as suggested by Michel. Signed-off-by:
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Alex Deucher authored
Make it clearer how these packets work. Acked-by:
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Alex Deucher authored
vega10 is the only soc15 asic at the moment so these warnings are invalid, but add a default case to silence the warnings. Fixes: 220ab9bd: "drm/amdgpu: soc15 enable (v3)" Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reported-by:
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- 04 Apr, 2017 2 commits
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Harry Wentland authored
On KB, KV, CZ we should read the vram width from integrated system table, if we can. The NOOFCHAN in MC_SHARED_CHMAP is not accurate. With this change we can enable two 4k displays on CZ again. This use case was broken sometime in January when we started looking at vram_width for bandwidth calculations instead of hardcoding this value. v2: Return 0 if integrated system info table is not available. Tested-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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Zhang, Jerry authored
break it out from the check parameters function. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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