An error occurred fetching the project authors.
- 02 May, 2013 1 commit
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Bharat Bhushan authored
We do not want to take single step and branch-taken debug exception in kernel exception code. But the address range check was not covering all kernel exception handlers address range. With this patch we defined the interrupt_end label which defines the end on kernel exception code. So now we check interrupt_base to interrupt_end range for not handling debug exception in kernel exception entry. Signed-off-by:
Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 12 Sep, 2012 2 commits
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Varun Sethi authored
Move the E.HV check and CPU_FTR_EMB_HV flag manipulation to the cpu setup code. Create a separate routine for E.HV ivors setup. Signed-off-by:
Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Zhao Chenhui authored
Add support to disable and re-enable individual cores at runtime on MPC85xx/QorIQ SMP machines. Currently support e500v1/e500v2 core. MPC85xx machines use ePAPR spin-table in boot page for CPU kick-off. This patch uses the boot page from bootloader to boot core at runtime. It supports 32-bit and 36-bit physical address. Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
Jin Qing <b24347@freescale.com> Signed-off-by:
Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 11 Jul, 2012 1 commit
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Stuart Yoder authored
Signed-off-by:
Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 10 Jul, 2012 1 commit
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Liu Yu authored
So that we can call it when improving SPE switch like book3e did for fp switch. Signed-off-by:
Liu Yu <yu.liu@freescale.com> Signed-off-by:
Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 30 Apr, 2012 1 commit
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Anton Blanchard authored
Use an empty inline instead of an empty function to implement giveup_altivec on book3e CPUs, similar to flush_altivec_to_thread. Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 08 Apr, 2012 2 commits
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Scott Wood authored
Add processor support for e500mc, using hardware virtualization support (GS-mode). Current issues include: - No support for external proxy (coreint) interrupt mode in the guest. Includes work by Ashish Kalra <Ashish.Kalra@freescale.com>, Varun Sethi <Varun.Sethi@freescale.com>, and Liu Yu <yu.liu@freescale.com>. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
Avi Kivity <avi@redhat.com>
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Scott Wood authored
DO_KVM will need to identify the particular exception type. There is an existing set of arbitrary numbers that Linux passes, but it's an undocumented mess that sort of corresponds to server/classic exception vectors but not really. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
Avi Kivity <avi@redhat.com>
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- 08 Mar, 2012 1 commit
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Benjamin Herrenschmidt authored
We currently turn interrupts back to their previous state before calling do_page_fault(). This can be annoying when debugging as a bad fault will potentially have lost some processor state before getting into the debugger. We also end up calling some generic code with interrupts enabled such as notify_page_fault() with interrupts enabled, which could be unexpected. This changes our code to behave more like other architectures, and make the assembly entry code call into do_page_faults() with interrupts disabled. They are conditionally re-enabled from within do_page_fault() in the same spot x86 does it. While there, add the might_sleep() test in the case of a successful trylock of the mmap semaphore, again like x86. Also fix a bug in the existing assembly where r12 (_MSR) could get clobbered by C calls (the DTL accounting in the exception common macro and DISABLE_INTS) in some cases. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> --- v2. Add the r12 clobber fix
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- 20 Dec, 2011 1 commit
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Suzuki Poulose authored
The current implementation of CONFIG_RELOCATABLE in BookE is based on mapping the page aligned kernel load address to KERNELBASE. This approach however is not enough for platforms, where the TLB page size is large (e.g, 256M on 44x). So we are renaming the RELOCATABLE used currently in BookE to DYNAMIC_MEMSTART to reflect the actual method. The CONFIG_RELOCATABLE for PPC32(BookE) based on processing of the dynamic relocations will be introduced in the later in the patch series. This change would allow the use of the old method of RELOCATABLE for platforms which can afford to enforce the page alignment (platforms with smaller TLB size). Changes since v3: * Introduced a new config, NONSTATIC_KERNEL, to denote a kernel which is either a RELOCATABLE or DYNAMIC_MEMSTART(Suggested by: Josh Boyer) Suggested-by:
Scott Wood <scottwood@freescale.com> Tested-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Suzuki K. Poulose <suzuki@in.ibm.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Josh Boyer <jwboyer@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linux ppc dev <linuxppc-dev@lists.ozlabs.org> Signed-off-by:
Josh Boyer <jwboyer@gmail.com>
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- 03 Nov, 2011 1 commit
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Matthew McClintock authored
Fix typo in comments introduced by: commit 6dece0eb Author: Scott Wood <scottwood@freescale.com> Date: Mon Jul 25 11:29:33 2011 +0000 powerpc/32: Pass device tree address as u64 to machine_init Signed-off-by:
Matthew McClintock <msm@freescale.com> cc: Scott Wood <scottwood@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 19 Sep, 2011 2 commits
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Scott Wood authored
u64 is used rather than phys_addr_t to keep things simple, as this is called from assembly code. Update callers to pass a 64-bit address in r3/r4. Other unused register assignments that were once parameters to machine_init are dropped. For FSL BookE, look up the physical address of the device tree from the effective address passed in r3 by the loader. This is required for situations where memory does not start at zero (due to AMP or IOMMU-less virtualization), and thus the IMA doesn't start at zero, and thus the device tree effective address does not equal the physical address. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Becky Bruce authored
Enable hugepages on Freescale BookE processors. This allows the kernel to use huge TLB entries to map pages, which can greatly reduce the number of TLB misses and the amount of TLB thrashing experienced by applications with large memory footprints. Care should be taken when using this on FSL processors, as the number of large TLB entries supported by the core is low (16-64) on current processors. The supported set of hugepage sizes include 4m, 16m, 64m, 256m, and 1g. Page sizes larger than the max zone size are called "gigantic" pages and must be allocated on the command line (and cannot be deallocated). This is currently only fully implemented for Freescale 32-bit BookE processors, but there is some infrastructure in the code for 64-bit BooKE. Signed-off-by:
Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 12 Jul, 2011 2 commits
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Scott Wood authored
Previously, these macros hardcoded THREAD_EVR0 as the base of the save area, relative to the base register passed. This base offset is now passed as a separate macro parameter, allowing reuse with other SPE save areas, such as used by KVM. Acked-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Alexander Graf <agraf@suse.de>
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yu liu authored
giveup_spe() saves the SPE state which is protected by MSR[SPE]. However, modifying SPEFSCR does not trap when MSR[SPE]=0. And since SPEFSCR is already saved/restored in _switch(), not all the callers want to save SPEFSCR again. Thus, saving SPEFSCR should not belong to giveup_spe(). This patch moves SPEFSCR saving to flush_spe_to_thread(), and cleans up the caller that needs to save SPEFSCR accordingly. Signed-off-by:
Liu Yu <yu.liu@freescale.com> Acked-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Alexander Graf <agraf@suse.de>
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- 23 Jun, 2011 1 commit
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Ashish Kalra authored
We expect this is actually faster, and we end up needing more space than we can get from the SPRGs in some instances. This is also useful when running as a guest OS - SPRGs4-7 do not have guest versions. 8 slots are allocated in thread_info for this even though we only actually use 4 of them - this allows space for future code to have more scratch space (and we know we'll need it for things like hugetlb). Signed-off-by:
Ashish Kalra <Ashish.Kalra@freescale.com> Signed-off-by:
Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 31 Mar, 2011 1 commit
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Lucas De Marchi authored
Fixes generated by 'codespell' and manually reviewed. Signed-off-by:
Lucas De Marchi <lucas.demarchi@profusion.mobi>
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- 29 Nov, 2010 1 commit
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Stephen Rothwell authored
Since STACK_FRAME_OVERHEAD is defined in asm/ptrace.h and that is ASSEMBER safe, we can just include that instead of going via asm-offsets.h. Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 14 Oct, 2010 1 commit
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Matthew McClintock authored
First we check to see if we are the first core booting up. This is accomplished by comparing the boot_cpuid with -1, if it is we assume this is the first core coming up. Secondly, we need to update the initial thread info structure to reflect the actual cpu we are running on otherwise smp_processor_id() and related functions will return the default initialization value of the struct or 0. Signed-off-by:
Matthew McClintock <msm@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 25 May, 2010 1 commit
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Sebastian Andrzej Siewior authored
This adds support kexec on FSL-BookE where the MMU can not be simply switched off. The code borrows the initial MMU-setup code to create the identical mapping mapping. The only difference to the original boot code is the size of the mapping(s) and the executeable address. The kexec code maps the first 2 GiB of memory in 256 MiB steps. This should work also on e500v1 boxes. SMP support is still not available. (Kumar: Added minor change to build to ifdef CONFIG_PPC_STD_MMU_64 some code that was PPC64 specific) Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 24 May, 2010 2 commits
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Sebastian Andrzej Siewior authored
This patch only moves the initial entry code which setups the mapping from what ever to KERNELBASE into a seperate file. No code change has been made here. Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Sebastian Andrzej Siewior authored
During boot we change the mapping a few times until we have a "defined" mapping. During this procedure a small 4KiB mapping is created and after that one a 64MiB. Currently the offset of the 4KiB page in that we run is zero because the complete startup up code is in first page which starts at RPN zero. If the code is recycled and moved to another location then its execution will fail because the start address in 64 MiB mapping is computed wrongly. It does not consider the offset to the page from the begin of the memory. This patch fixes this. Usually (system boot) r25 is zero so this does not change anything unless the code is recycled. Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 17 May, 2010 1 commit
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Li Yang authored
In CONFIG_PTE_64BIT the PTE format has unique permission bits for user and supervisor execute. However on !CONFIG_PTE_64BIT we overload the supervisor bit to imply user execute with _PAGE_USER set. This allows us to use the same permission check mask for user or supervisor code on !CONFIG_PTE_64BIT. However, on CONFIG_PTE_64BIT we map _PAGE_EXEC to _PAGE_BAP_UX so we need a different permission mask based on the fault coming from a kernel address or user space. Without unique permission masks we see issues like the following with modules: Unable to handle kernel paging request for instruction fetch Faulting instruction address: 0xf938d040 Oops: Kernel access of bad area, sig: 11 [#1] Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
Jin Qing <b24347@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 13 May, 2010 1 commit
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Li Yang authored
In CONFIG_PTE_64BIT the PTE format has unique permission bits for user and supervisor execute. However on !CONFIG_PTE_64BIT we overload the supervisor bit to imply user execute with _PAGE_USER set. This allows us to use the same permission check mask for user or supervisor code on !CONFIG_PTE_64BIT. However, on CONFIG_PTE_64BIT we map _PAGE_EXEC to _PAGE_BAP_UX so we need a different permission mask based on the fault coming from a kernel address or user space. Without unique permission masks we see issues like the following with modules: Unable to handle kernel paging request for instruction fetch Faulting instruction address: 0xf938d040 Oops: Kernel access of bad area, sig: 11 [#1] Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
Jin Qing <b24347@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 19 Mar, 2010 1 commit
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Márton Németh authored
When printk() is disabled (CONFIG_PRINTK) at menu item General setup -> Configure standard kernel features (for small systems) -> Enable support for printk then there should be no printk() calls at all. Signed-off-by:
Márton Németh <nm127@freemail.hu> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 17 Mar, 2010 1 commit
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Kumar Gala authored
We shouldn't be always setting 'M' in the TLB entry since its reasonable for somethings to be mapped non-coherent. The PTE should have 'M' set properly. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 18 Feb, 2010 1 commit
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Sebastian Andrzej Siewior authored
24 is offset between the opcode past bl and past rfi. This makes it more obvious. Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 20 Nov, 2009 1 commit
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Kumar Gala authored
Re-write the code so its more standalone and fixed some issues: * Bump'd # of CAM entries to 64 to support e500mc * Make the code handle MAS7 properly * Use pr_cont instead of creating a string as we go Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 02 Sep, 2009 1 commit
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Kumar Gala authored
Switch to using the Power ISA defined PTE format when we have a 64-bit PTE. This makes the code handling between fsl-booke and book3e-64 similiar for TLB faults. Additionally this lets use take advantage of the page size encodings and full permissions that the HW PTE defines. Also defined _PMD_PRESENT, _PMD_PRESENT_MASK, and _PMD_BAD since the 32-bit ppc arch code expects them. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 27 Aug, 2009 1 commit
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Benjamin Herrenschmidt authored
This is an attempt at cleaning up a bit the way we handle execute permission on powerpc. _PAGE_HWEXEC is gone, _PAGE_EXEC is now only defined by CPUs that can do something with it, and the myriad of #ifdef's in the I$/D$ coherency code is reduced to 2 cases that hopefully should cover everything. The logic on BookE is a little bit different than what it was though not by much. Since now, _PAGE_EXEC will be set by the generic code for executable pages, we need to filter out if they are unclean and recover it. However, I don't expect the code to be more bloated than it already was in that area due to that change. I could boast that this brings proper enforcing of per-page execute permissions to all BookE and 40x but in fact, we've had that now for some time as a side effect of my previous rework in that area (and I didn't even know it :-) We would only enable execute permission if the page was cache clean and we would only cache clean it if we took and exec fault. Since we now enforce that the later only work if VM_EXEC is part of the VMA flags, we de-fact already enforce per-page execute permissions... Unless I missed something Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 20 Aug, 2009 1 commit
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Benjamin Herrenschmidt authored
The kernel uses SPRG registers for various purposes, typically in low level assembly code as scratch registers or to hold per-cpu global infos such as the PACA or the current thread_info pointer. We want to be able to easily shuffle the usage of those registers as some implementations have specific constraints realted to some of them, for example, some have userspace readable aliases, etc.. and the current choice isn't always the best. This patch should not change any code generation, and replaces the usage of SPRN_SPRGn everywhere in the kernel with a named replacement and adds documentation next to the definition of the names as to what those are used for on each processor family. The only parts that still use the original numbers are bits of KVM or suspend/resume code that just blindly needs to save/restore all the SPRGs. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 26 Apr, 2009 1 commit
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Tim Abbott authored
This has the consequence of changing the section name use for head code from ".text.head" to ".head.text". Since this commit changes all users in the architecture, this change should be harmless. Signed-off-by:
Tim Abbott <tabbott@mit.edu> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by:
Sam Ravnborg <sam@ravnborg.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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- 23 Feb, 2009 1 commit
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Kumar Gala authored
The e500mc supports the new msgsnd/doorbell mechanisms that were added in the Power ISA 2.05 architecture. We use the normal level doorbell for doing SMP IPIs at this point. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 12 Feb, 2009 1 commit
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Kumar Gala authored
The Power ISA 2.06 added power of two page sizes to the embedded MMU architecture. Its done it such a way to be code compatiable with the existing HW. Made the minor code changes to support both power of two and power of four page sizes. Also added some new MAS bits and macros that are defined as part of the 2.06 ISA. Renamed some things to use the 'Book-3e' concept to convey the new MMU that is based on the Freescale Book-E MMU programming model. Note, its still invalid to try and use a page size that isn't supported by cpu. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 29 Jan, 2009 1 commit
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Kumar Gala authored
We currently have a few variants of fsl-booke processors (e500v1, e500v2, e500mc, and e200). They all have minor differences that we had previously been handling via ifdefs. To move towards having this support the following changes have been made: * PID1, PID2 only exist on e500v1 & e500v2 and should not be accessed on e500mc or e200. We use MMUCFG[NPIDS] to determine which case we are since we only touch PID1/2 in extremely early init code. * Not all IVORs exist on all the processors so introduce cpu_setup functions for each variant to setup the proper IVORs that are either unique or exist but have some variations between the processors Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 13 Jan, 2009 1 commit
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Kumar Gala authored
We use Doorbell interrupts for IPIs and thus we need to make sure we aren't interrupted in the process of processing the IPI. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Acked-by:
Dave Liu <daveliu@freescale.com>
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- 07 Jan, 2009 2 commits
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Trent Piepho authored
This is a global variable defined in fsl_booke_mmu.c with a value that gets initialized in assembly code in head_fsl_booke.S. It's never used. If some code ever does want to know the number of entries in TLB1, then "numcams = mfspr(SPRN_TLB1CFG) & 0xfff", is a whole lot simpler than a global initialized during kernel boot from assembly. Signed-off-by:
Trent Piepho <tpiepho@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Trent Piepho authored
Some assembly code in head_fsl_booke.S hard-coded the size of struct tlbcam to 20 when it indexed the TLBCAM table. Anyone changing the size of struct tlbcam would not know to expect that. The kernel already has a system to get the size of C structures into assembly language files, asm-offsets, so let's use it. The definition of the struct gets moved to a header, so that asm-offsets.c can include it. Signed-off-by:
Trent Piepho <tpiepho@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 21 Dec, 2008 1 commit
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Benjamin Herrenschmidt authored
We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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- 03 Dec, 2008 1 commit
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Kumar Gala authored
Added 85xx specifc smp_ops structure. We use ePAPR style boot release and the MPIC for IPIs at this point. Additionally added routines for secondary cpu entry and initializtion. Signed-off-by:
Andy Fleming <afleming@freescale.com> Signed-off-by:
Trent Piepho <tpiepho@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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