- 17 Feb, 2013 27 commits
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Gabor Juhos authored
This is needed for multiple PCI bus support. Signed-off-by:
Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4913/Signed-off-by:
John Crispin <blogic@openwrt.org>
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Gabor Juhos authored
The pci_load_of_ranges function is only available if CONFIG_OF is selected. If the function is used without CONFIG_OF being enabled it will cause a build error. Add a dummy inline function to avoid this. Signed-off-by:
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Gabor Juhos authored
The IO and memory resources of a PCI controller might already have a parent resource set when they are passed to 'register_pci_controller'. If the parent resource is set, the request_resource call will fail due to resource conflict and the current code will not be able to register the PCI controller. Use the parent resource if it is available in the request_resource call to avoid the isssue. Signed-off-by:
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Gabor Juhos authored
The functions are unused now, so remove them. Signed-off-by:
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Gabor Juhos authored
The pci-ar71xx and pci-ar724x drivers were converted into platform drivers. Register the corresponding platform devices for the PCI controllers instead of using the ar7{1x,24}x_pcibios_init functions. Signed-off-by: -
Gabor Juhos authored
The constants will be used by a subsequent patch. Signed-off-by:
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Gabor Juhos authored
The patch converts the pci-ar71xx driver into a platform driver. This makes it possible to register the PCI controller as a plain platform device. Signed-off-by:
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Gabor Juhos authored
The patch converts the pci-ar724x driver into a platform driver. This makes it possible to register the PCI controller as a plain platform device. Signed-off-by:
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Gabor Juhos authored
Convert the ralink IRQ code to make use of the new MIPS IRQ controller OF mappings. Signed-off-by:
David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4900/
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Gabor Juhos authored
Add code to load a irq_domain for the MIPS IRQ controller from a devicetree file. Signed-off-by:
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John Crispin authored
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John Crispin authored
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John Crispin authored
Add the Kbuild symbols and Makefiles needed to actually build the ralink code from this series Signed-off-by:
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John Crispin authored
This adds the devicetree file that describes the rt305x evaluation kit. Signed-off-by:
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John Crispin authored
Add support code for rt3050, rt3052, rt3350, rt3352 and rt5350 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by:
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John Crispin authored
Add the code needed to make early printk work. Signed-off-by:
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John Crispin authored
Until there is a generic MIPS way of handing the DTB over from bootloader to kernel we rely on a built in devicetrees. The OF code also remaps those register ranges that we use global in our drivers. Signed-off-by:
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John Crispin authored
These SoCs have a limited number of fixed rate clocks. Add support for the clk and clkdev api. Signed-off-by:
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John Crispin authored
Add minimal code to handle commandlines. Signed-off-by:
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John Crispin authored
Resetting these SoCs requires no real magic. The code is straight forward. Signed-off-by:
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John Crispin authored
All of the Ralink Wifi SoC currently supported by this series share the same interrupt controller (INTC). Signed-off-by:
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John Crispin authored
Before we start adding the platform code we add the common include files. Signed-off-by:
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John Crispin authored
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Gabor Juhos authored
The current code uses multiple if statements for demultiplexing the different interrupt sources. Additionally, the MISC interrupt controller has 32 interrupt sources and the current code does not handles all of them. Get rid of the if statements and process all interrupt sources in a loop to fix these issues. Signed-off-by:
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Gabor Juhos authored
Make ath79_gpio_function_{en,dis}able to be wrappers around ath79_gpio_function_setup. Signed-off-by: -
Gabor Juhos authored
GPIO function selection is not working on the AR934x SoCs because the offset of the function selection register is different on those. Add a helper routine which returns the correct register address based on the SoC type, and use that in the 'ath79_gpio_function_*' routines. Signed-off-by:
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Steven J. Hill authored
Add new clocksource that uses the counter present on the MIPS Global Interrupt Controller. Signed-off-by:
Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4681/Signed-off-by:
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- 16 Feb, 2013 13 commits
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Steven J. Hill authored
Simplify the DSP macros for vanilla (non-microMIPS) kernels and toolchains that do not support the DSP ASEs. Signed-off-by:
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Steven J. Hill authored
Add macros to support the DSP ASE with microMIPS kernels when the toolchain does not have support. Signed-off-by:
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Steven J. Hill authored
Newer toolchains support the DSP and DSP Rev2 instructions. This patch performs a check for that support and adds compiler and assembler flags for only the files that need use those instructions. Signed-off-by:
Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4752/Signed-off-by:
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Steven J. Hill authored
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Steven J. Hill authored
Clean up standard header text and remove unused #define. Signed-off-by:
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Jayachandran C authored
On a multi-chip XLP board, each node can have 4 PCIe links. Update XLP PCI code to initialize PCIe on all the nodes. Signed-off-by:
Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4803/Signed-off-by:
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Jayachandran C authored
On multi-chip boards, the first core on slave SoCs may take much more time to wakeup. Add code to wait for the core to come up before proceeding with the rest of the boot up. Update xlp_wakeup_core to also skip the boot node and the boot CPU initialization which is already complete. Signed-off-by:
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Jayachandran C authored
Doing calibrate delay on a hardware thread will be inaccurate since it depends on the load on other threads in the core. It will also slow down the boot process when done for 128 hardware threads. Switch to a pre-computed loops per jiffy based on the core frequency. The value is computed based on the core frequency and roughly matches the value calculated by calibrate_delay(). Signed-off-by:
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Jayachandran C authored
TLB and COP0 hazards are handled in hardware for Netlogic XLR/XLS SoCs. Update hazards.h to pick more optimal set of definitions when compiling for XLR/XLS. Signed-off-by:
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Jayachandran C authored
Reading PCI extended register at 0x255 on a bridge will hang if there is no device connected on the link. Make PCI read routine skip this register. Signed-off-by:
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Jayachandran C authored
The XLR/XLS/XLP PIC has a 8 countdown timers which run at the PIC frequencey. One of these can be used as a clocksource to provide timestamps that is common across cores. This can be used in place of the count/compare clocksource which is per-CPU. On XLR/XLS PIC registers are 32-bit, so we just use the lower 32-bits of the PIC counter. On XLP, the whole 64-bit can be used. Provide common macros and functions for PIC timer registers on XLR/XLS and XLP, and use them to register a PIC clocksource. Signed-off-by:
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Jayachandran C authored
Since we now use r4k cache code for Netlogic XLP, it is better to split L1 icache among the active threads, so that threads won't step on each other while flushing icache. The L1 dcache is already split among the threads in the core. Signed-off-by:
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Jayachandran C authored
Rename function xlp_enable_pci_bswap() to xlp_config_pci_bswap(), which is a better description for its functionality. When compiled in big-endian mode, xlp_config_pci_bswap() will configure the PCIe links to byteswap. In little-endian mode, no swap configuration is needed for the PCIe controller, and the function is empty. Signed-off-by:
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