1. 07 Apr, 2016 25 commits
  2. 06 Apr, 2016 15 commits
    • Stefan Assmann's avatar
      e1000: call ndo_stop() instead of dev_close() when running offline selftest · 1f2f83f8
      Stefan Assmann authored
      Calling dev_close() causes IFF_UP to be cleared which will remove the
      interfaces routes and some addresses. That's probably not what the user
      intended when running the offline selftest. Besides this does not happen
      if the interface is brought down before the test, so the current
      behaviour is inconsistent.
      Instead call the net_device_ops ndo_stop function directly and avoid
      touching IFF_UP at all.
      Signed-off-by: default avatarStefan Assmann <sassmann@kpanic.de>
      Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      1f2f83f8
    • David S. Miller's avatar
      Merge branch 'mlxsw-dcb' · 58a01d4d
      David S. Miller authored
      Jiri Pirko says:
      
      ====================
      mlxsw: Introduce support for Data Center Bridging
      
      Ido says:
      
      This patchset introduces support for Quality of Service (QoS) as part of the
      IEEE Data Center Bridiging (DCB) standards.
      
      Patches 1-9 do the required device initialization. Specifically, patches 1-6
      initialize the ports' headroom buffers, which are used at ingress to store
      incoming packets while they go through the switch's pipeline. Patches 7-9
      complete them by initializing the egress scheduling.
      
      The pipeline mentioned above determines the packet's egress port(s) and
      traffic class. Ideally, once out of the pipeline the packet moves to the
      switch's shared buffer (to be introduced in Jiri's patchset, currently
      default values are used) and scheduled for transmission according to its
      traffic class. The egress scheduling is configured according to the 802.1Qaz
      standard, which is part of the DCB infrastructure supported by Linux. This
      is introduced in patches 10-12.
      
      Even after going through the pipeline packets are not always eligible to
      enter the shared buffer. This is determined by the amount of available space
      and the quotas associated with the packet. However, if flow control is
      enabled and the packet is associated with the lossless flow, then it will
      stay in the headroom and won't be discarded. This is introduced in patches
      13-17.
      
      Please check individual commit messages for more info, as I tried to keep
      them pretty detailed.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      58a01d4d
    • Ido Schimmel's avatar
      mlxsw: spectrum: Add IEEE 802.1Qbb PFC support · d81a6bdb
      Ido Schimmel authored
      Implement the appropriate DCB ops and allow a user to configure certain
      traffic classes as lossless.
      
      The operation configures PFC for both the egress (respecting PFC frames)
      and ingress (sending PFC frames) parts of the port.
      
      At egress, when a PFC frame is received for a PFC enabled priority, then
      all the priorities mapped to the same TC are stopped.
      
      At ingress, the priority group (PG) buffers to which the enabled PFC
      priorities are mapped are configured to be lossless. PFC frames will be
      transmitted when the Xoff threshold is crossed.
      
      The user-supplied delay parameter is used to determine the PG's size
      according to the following formula:
      
      PG_SIZE = PG_SIZE_LOSSY + delay * CELL_FACTOR + MTU
      
      In the worst case scenario the delay will be made up of packets that
      are all of size CELL_SIZE + 1, which means each packet will require
      almost twice its true size when buffered in the switch. We therefore
      multiply this value by the "cell factor", which is close to 2.
      
      Another MTU is added in case the transmitting host already started
      transmitting a maximum length frame when the PFC packet was received.
      
      As with PAUSE enabled ports, when the port's MTU is changed both the
      PGs' size and threshold are adjusted accordingly.
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      d81a6bdb
    • Ido Schimmel's avatar
      mlxsw: reg: Introduce per priority counters · 34dba0a5
      Ido Schimmel authored
      We are going to add support for PFC as part of DCB ops, which requires us
      to report the number of PFC frames sent and received per priority.
      
      Add per priority counters in order to report number of PFC frames sent
      and received per priority.
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      34dba0a5
    • Ido Schimmel's avatar
      mlxsw: spectrum: Add support for PAUSE frames · 9f7ec052
      Ido Schimmel authored
      When a packet ingress the switch it's placed in its assigned priority
      group (PG) buffer in the port's headroom buffer while it goes through
      the switch's pipeline. After going through the pipeline - which
      determines its egress port(s) and traffic class - it's moved to the
      switch's shared buffer awaiting transmission.
      
      However, some packets are not eligible to enter the shared buffer due to
      exceeded quotas or insufficient space. Marking their associated PGs as
      lossless will cause the packets to accumulate in the PG buffer. Another
      reason for packets accumulation are complicated pipelines (e.g.
      involving a lot of ACLs).
      
      To prevent packets from being dropped a user can enable PAUSE frames on
      the port. This will mark all the active PGs as lossless and set their
      size according to the maximum delay, as it's not configured by user.
      
                               +----------------+   +
                               |                |   |
                               |                |   |
                               |                |   |
                               |                |   |
                               |                |   |
                               |                |   | Delay
                               |                |   |
                               |                |   |
                               |                |   |
                               |                |   |
                               |                |   |
          Xon/Xoff threshold   +----------------+   +
                               |                |   |
                               |                |   | 2 * MTU
                               |                |   |
                               +----------------+   +
      
      The delay (612 [Cells]) was calculated according to worst-case scenario
      involving maximum MTU and 100m cables.
      
      After marking the PGs as lossless the device is configured to respect
      incoming PAUSE frames (Rx PAUSE) and generate PAUSE frames (Tx PAUSE)
      according to user's settings.
      
      Whenever the port's headroom configuration changes we take into account
      the PAUSE configuration, so that we correctly set the PG's type (lossy /
      lossless), size and threshold. This can happen when:
      
      a) The port's MTU changes, as it directly affects the PG's size.
      
      b) A PG is created following user configuration, by binding a priority
      to it.
      
      Note that the relevant SUPPORTED flags were already mistakenly set by
      the driver before this commit.
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9f7ec052
    • Ido Schimmel's avatar
      mlxsw: reg: Add lossless settings for PBMC register · 155f9de2
      Ido Schimmel authored
      When configuring PAUSE frames and PFC we'll need to configure the
      Xon/Xoff threshold for the priority group (PG) buffers.
      
      Add the Xon/Xoff threshold fields to the PBMC register so that we can
      configure these when needed.
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      155f9de2
    • Ido Schimmel's avatar
      mlxsw: reg: Add Port Flow Control Configuration register · 6f253d83
      Ido Schimmel authored
      Add the Port Flow Control Configuration (PFCC) register, which
      configures both flow control and Priority-based Flow Control (PFC).
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6f253d83
    • Ido Schimmel's avatar
      mlxsw: spectrum: Allow setting maximum rate for a TC · cc7cf517
      Ido Schimmel authored
      Allow a user to set maximum rate for a particular TC using DCB ops.
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      cc7cf517
    • Ido Schimmel's avatar
      mlxsw: spectrum: Add IEEE 802.1Qaz ETS support · 8e8dfe9f
      Ido Schimmel authored
      Implement the appropriate DCB ops and allow a user to configure:
      	* Priority to traffic class (TC) mapping with a total of 8
      	  supported TCs
      	* Transmission selection algorithm (TSA) for each TC and the
      	  corresponding weights in case of weighted round robin (WRR)
      
      As previously explained, we treat the priority group (PG) buffer in the
      port's headroom as the ingress counterpart of the egress TC. Therefore,
      when a certain priority to TC mapping is configured, we also configure
      the port's headroom buffer.
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8e8dfe9f
    • Ido Schimmel's avatar
      mlxsw: spectrum: Introduce support for Data Center Bridging (DCB) · f00817df
      Ido Schimmel authored
      Introduce basic infrastructure for DCB and add the missing ops in
      following patches.
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f00817df
    • Ido Schimmel's avatar
      mlxsw: spectrum: Initialize egress scheduling · 90183b98
      Ido Schimmel authored
      Before introducing support for DCB ops we should first make sure we
      initialize the relevant parts in the device correctly. Specifically, the
      egress scheduling.
      
      The device supports a superset of the 802.1Qaz standard with 4 hierarchy
      levels that can be linked to each other in multiple ways and with
      different transmission selection algorithms (TSA) employed between them.
      
      However, since we only intend to support the 802.1Qaz standard we
      flatten the hierarchies and let the user configure via DCB ops the TSA
      and max rate shaper at the subgroup hierarchy (see figure below) and the
      mapping between switch priority to traffic class. By default, all switch
      priorities are mapped to traffic class 0, strict priority is employed
      and max shaper is disabled.
      
      Default configuration:
      
               switch priority 0      ...         switch priority 7
                       +                                  +
                       |                                  |
                       +----------------------------------+
                       |
                    +--v--+                          +-----+
      Traffic Class |     |                          |     |
        Hierarchy   | TC0 |           ...            | TC7 |
                    |     |                          |     |
                    +--+--+                          +--+--+
                       |                                |
                    +--v--+                          +--v--+
        Subgroup    | SG0 |                          | SG7 |
        Hierarchy   |     |                          |     |
                    +-----+                          +-----+
                    | TSA |                          | TSA |
                    +-----+           ...            +-----+
                    | MAX |                          | MAX |
                    +--+--+                          +--+--+
                       |                                |
                       +---------------+----------------+
                                       |
                                    +--v--+
                            Group   |     |
                          Hierarchy | GR0 |
                                    |     |
                                    +--+--+
                                       |
                                    +--v--+
                            Port    |     |
                          Hierarchy | PR0 |
                                    |     |
                                    +-----+
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      90183b98
    • Ido Schimmel's avatar
      mlxsw: reg: Add QoS Switch Traffic Class Table register · 2c63a555
      Ido Schimmel authored
      As part of DCB ops we'll have to configure the priority to traffic class
      mapping of a port.
      
      Add the QoS Switch Traffic Class Table (QTCT) register, which configures
      the mapping between the packet switch priority and traffic class on the
      transmit port.
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      2c63a555
    • Ido Schimmel's avatar
      mlxsw: reg: Add QoS ETS Element Configuration register · b9b7cee4
      Ido Schimmel authored
      We are going to introduce support for DCB, so we need to be able to
      configure the traffic selection algorithm (TSA) used by each traffic
      class (TC), as well as the bandwidth percentage allocated to each TC in
      case of ETS.
      
      Add the QoS ETS Element Configuration register, which controls the
      above parameters.
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b9b7cee4
    • Ido Schimmel's avatar
      mlxsw: spectrum: Set port's shared buffer size to 0 · d6b7c13b
      Ido Schimmel authored
      In addition to the priority group (PG) buffers in the headroom, the
      device enables the allocation of headroom shared buffer, which can
      be shared between different PGs.
      
      However, we are not going to use the headroom shared buffer and instead
      allow the user to use its size for PGs or the switch's shared buffer.
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      d6b7c13b
    • Ido Schimmel's avatar
      mlxsw: reg: Use correct PBMC register length · 7ad7cd61
      Ido Schimmel authored
      The last field of the PBMC register is at offset 0x64 and its size is
      0x8, so the correct register's length is 0x6C bytes.
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      7ad7cd61