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  1. 27 Nov, 2007 15 commits
  3. 26 Nov, 2007 15 commits
    • Joe Perches's avatar
      [MIPS] vpe: Add missing "space" · b1e3afa0
      Joe Perches authored 
      Signed-off-by: default avatarJoe Perches <joe@perches.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      b1e3afa0
    • Richard Knutsson's avatar
      [MIPS] Compliment va_start() with va_end(). · 8142294d
      Richard Knutsson authored 
      Signed-off-by: default avatarRichard Knutsson <ricknu-0@student.ltu.se>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      8142294d
    • Thomas Bogendoerfer's avatar
      [MIPS] IP22: Fix broken eeprom access by using __raw_readl/__raw_writel · 5b3af8f1
      Thomas Bogendoerfer authored 
      Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      5b3af8f1
    • Thomas Bogendoerfer's avatar
      [MIPS] IP22: Fix broken EISA interrupt setup by switching to generic i8259 · 68de4803
      Thomas Bogendoerfer authored 
      Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      68de4803
    • Ralf Baechle's avatar
      [MIPS] 64-bit Sibyte kernels need DMA32. · cce335ae
      Ralf Baechle authored 
      Sibyte SOCs only have 32-bit PCI.  Due to the sparse use of the address
space only the first 1GB of memory is mapped at physical addresses
below 1GB.  If a system has more than 1GB of memory 32-bit DMA will
not be able to reach all of it.

For now this patch is good enough to keep Sibyte users happy but it seems
eventually something like swiotlb will be needed for Sibyte.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      cce335ae
    • Ralf Baechle's avatar
      [MIPS] Only build r4k clocksource for systems that work ok with it. · 940f6b48
      Ralf Baechle authored 
      In particular as-is it's not suited for multicore and mutiprocessors
systems where there is on guarantee that the counter are synchronized
or running from the same clock at all.  This broke Sibyte and probably
others since the "[MIPS] Handle R4000/R4400 mfc0 from count register."
commit.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      940f6b48
    • Ralf Baechle's avatar
      [MIPS] Handle R4000/R4400 mfc0 from count register. · 5aa85c9f
      Ralf Baechle authored 
      The R4000 and R4400 have an errata where if the cp0 count register is read
in the exact moment when it matches the compare register no interrupt will
be generated.

This bug may be triggered if the cp0 count register is being used as
clocksource and the compare interrupt as clockevent.  So a simple
workaround is to avoid using the compare for both facilities on the
affected CPUs.

This is different from the workaround suggested in the old errata documents;
at some opportunity probably the official version should be implemented
and tested.  Another thing to find out is which processor versions
exactly are affected.  I only have errata documents upto R4400 V3.0
available so for the moment the code treats all R4000 and R4400 as broken.

This is potencially a problem for some machines that have no other decent
clocksource available; this workaround will cause them to fall back to
another clocksource, worst case the "jiffies" source.
      5aa85c9f
    • Ralf Baechle's avatar
      [MIPS] Fix possible hang in LL/SC futex loops. · 0f67e90e
      Ralf Baechle authored 
      The LL / SC loops in __futex_atomic_op() have the usual fixups necessary
for memory acccesses to userspace from kernel space installed:

        __asm__ __volatile__(
        "       .set    push                            \n"
        "       .set    noat                            \n"
        "       .set    mips3                           \n"
        "1:     ll      %1, %4  # __futex_atomic_op     \n"
        "       .set    mips0                           \n"
        "       " insn  "                               \n"
        "       .set    mips3                           \n"
        "2:     sc      $1, %2                          \n"
        "       beqz    $1, 1b                          \n"
        __WEAK_LLSC_MB
        "3:                                             \n"
        "       .set    pop                             \n"
        "       .set    mips0                           \n"
        "       .section .fixup,\"ax\"                  \n"
        "4:     li      %0, %6                          \n"
        "       j       2b                              \n"	<-----
        "       .previous                               \n"
        "       .section __ex_table,\"a\"               \n"
        "       "__UA_ADDR "\t1b, 4b                    \n"
        "       "__UA_ADDR "\t2b, 4b                    \n"
        "       .previous                               \n"
        : "=r" (ret), "=&r" (oldval), "=R" (*uaddr)
        : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)
        : "memory");

The branch at the end of the fixup code, it goes back to the SC
instruction, no matter if the fault was first taken by the LL or SC
instruction resulting in an endless loop which will only terminate if
the address become valid again due to another thread setting up an
accessible mapping and the CPU happens to execute the SC instruction
successfully which due to the preceeding ERET instruction of the fault
handler would only happen if UNPREDICTABLE instruction behaviour of the
SC instruction without a preceeding LL happens to favor that outcome.
But normally processes are nice, pass valid arguments and we were just
getting away with this.

Thanks to Kaz Kylheku <kaz@zeugmasystems.com> for providing the original
report and a test case.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      0f67e90e
    • Ralf Baechle's avatar
      [MIPS] Fix context DSP context / TLS pointer switching bug for new threads. · 07500b0d
      Ralf Baechle authored 
      A new born thread starts execution not in schedule but rather in
ret_from_fork which results in it bypassing the part of the code to
load a new context written in C which are the DSP context and the
userlocal register which Linux uses for the TLS pointer.  Frequently
we were just getting away with this bug for a number of reasons:

 o Real world application scenarios are very unlikely to use clone or fork
   in blocks of DSP code.
 o Linux by default runs the child process right after the fork, so the
   child by luck will find all the right context in the DSP and userlocal
   registers.
 o So far the rdhwr instruction was emulated on all hardware so userlocal
   wasn't getting referenced at all and the emulation wasn't suffering
   from the issue since it gets it's value straight from the thread's
   thread_info.

Fixed by moving the code to load the context from switch_to() to
finish_arch_switch which will be called by newborn and old threads.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      07500b0d
    • Ralf Baechle's avatar
      [MIPS] IP32: More interrupt renumbering fixes. · 98ce4721
      Ralf Baechle authored 
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      98ce4721
    • Ralf Baechle's avatar
      [MIPS] time: MIPSsim's plat_time_init doesn't need to be irq safe. · 526a6770
      Ralf Baechle authored 
      It's running early during the bootup process so interrupts are still off.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      526a6770
    • Ralf Baechle's avatar
      [MIPS] time: Fix negated condition in cevt-r4k driver. · aea68639
      Ralf Baechle authored 
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      aea68639
    • Ralf Baechle's avatar
      [MIPS] Fix pcspeaker build. · cfb6f260
      Ralf Baechle authored 
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      cfb6f260
    • Tejun Heo's avatar
      libata: bump transfer chunk size if it's odd · e190222d
      Tejun Heo authored 
      None of the drives I have follows what the standard says about
transfer chunk size.  Of the four SATA and six PATA ATAPI devices
tested, four ignore transfer chunk size completely and the ones which
honor it don't behave according to the spec when it's odd.

According to the spec, transfer chunk size can be odd if the amount of
data to transfer equals or is smaller than the chunk size and the
device can indicate the same odd number and transfer the whole thing
at one go with a pad byte appended.  However, in reality, none of the
drives I have does that.  They all indicate and transfer even number
of bytes one byte shorter than the chunk size first; then indicate and
transfer two bytes, which is clearly out of spec.

In addition to unnecessary second PIO data phase, this also creates a
weird problem when combined with SATA controllers which perform PIO
via DMA.  Some of these controllers use actualy number of bytes
received to update DMA pointer so chunks which are sized 4n + 2 makes
DMA pointer off by two bytes.  This causes data corruption and buffer
overruns.

This patch rounds nbytes up to the nearest even number such that ATAPI
devices don't split data transfer for the last odd byte.  This
shouldn't confuse controllers which depend on transfer chunk size as
devices will report the rounded-up number, actually transfer that much
and padding buffer is there to receive them.
Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      e190222d
    • sonic zhang's avatar
      libata: Return proper ATA INT status in pata_bf54x driver · dc86f6d4
      sonic zhang authored 
      INT status can be OR.
Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      dc86f6d4
  5. 25 Nov, 2007 2 commits
  7. 24 Nov, 2007 8 commits
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