- 29 May, 2014 40 commits
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Russell King authored
ux500 can't write to any of the secure registers on the L2C controllers, so provide a dummy handler which ignores all writes. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. We can remove the .init_machine as it becomes the same as the generic version. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. This also allows us to eliminate the .init_machine function as this becomes the same as the generic version. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Add better commentry about the L2 cache requirements on these platforms. Unfortunately, the auxiliary control register is not pre-set to indicate the correct cache parameters, so we have to manually program these. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. Along with this change, we can delete l2x0.c from prima2. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Sekhar Nori authored
Add support for L2 cache controller (PL310) on AM437x SoC. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Sekhar Nori authored
Get rid of init call to initialize L2 cache. Instead use the init_early machine hook. This helps in using the initialization routine across SoCs without the need of ugly cpu_is_*() checks. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Sekhar Nori authored
L2 cache initialization for OMAP4 redundantly sets the cache policy to Round-Robin. This is not needed since thats the PL310 default anyway. Removing this reduces the number of platform specific aux control settings. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Avoid reading directly from the L2 registers in platform code. The L2 code will have already saved the register values itself into the l2x0_saved_regs structure, so platform code should just move these values to where they're required. This is safe because the L2x0 will have been initialised by an early initcall, whereas the OMAP4 PM code is initialised late. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Since we now always enable NS access to the unlock registers, this can be removed from OMAP4. Remove the NS access bit for the interrupt registers from OMAP4 as well - nothing in the kernel accesses that yet, and we can add it in core code when we have the need. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Now that OMAP2 uses the write_sec method, we don't need to enable the L2 cache in OMAP2 specific code; this can be done via the normal mechanisms in the L2C code. Remove the OMAP2 specific code. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
With the write_sec method, we no longer need to override the default L2C disable method, and we no longer need the L2C set_debug method. Both of these can be handled via the write_sec method. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. This also allows us to eliminate the .init_machine function as it is identical to the generic version. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. Since the .init_irq method only calls irqchip_init(), we can remove that too as the generic code will take care of that. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Now that we handle this in core code, we don't need platforms enabling the low power modes directly. Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Now that highbank uses the write_sec method, we don't need to enable the L2 cache in SoC specific code; this can be done via the normal mechanisms in the L2C code. Checking with Rob Herring: > > Can we kill the "highbank_smc1(0x102, 0x1);" here? That means > > l2x0_of_init() will see the L2 cache disabled, and will try to enable > > it via the write_sec hook, so it should do the right thing. > > Yes, that should work. You should be able to just call l2x0_of_init > unconditionally. The condition was really to just avoid the smc on > Midway which does get handled on h/w, but not if running virtualized. So also drop the DT check too. I'm leaving the config check in place so that if L2 is disabled, the write_sec hook can be optimised away. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
With the write_sec method, we no longer need to override the default L2C disable method. This can be handled via the write_sec method instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
exynos was unconditionally calling the L2 cache initialisation from an early_initcall. This breaks multiplatform kernels. Thankfully, converting to generic l2c initialisation fixes this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. We can remove the explicit machine init too as this becomes identical to the generic version. Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. We can remove the explicit machine init too as this becomes identical to the generic version. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Provide a common assembly implementation for PL310 resume code. Certain platforms need to re-initialise the L2C cache early as it may preserve data across a S2RAM cycle, and therefore must be enabled along with the L1 cache and MMU. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Add a hook into the core ARM code to perform L2 cache initialisation in a platform independent manner. Platforms still get to indicate their auxiliary control register values and mask, but the initialisation call will now be made from generic code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Since we always write to these during the cache initialisation, it is a good idea to always have the non-secure access bit set. Set it in core code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Always enable the L2C low power modes on L2C-310 R3P0 and newer parts. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Since we now automatically enable early BRESP in core L2C-310 code when we detect a Cortex-A9, we don't need platforms/SoCs to set this bit explicitly. Instead, they should seek to preserve the value of bit 30 in the auxiliary control register. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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