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  1. 07 Sep, 2016 6 commits
    • Eric Anholt's avatar
      clk: bcm2835: Skip PLLC clocks when deciding on a new clock parent · 67615c58
      Eric Anholt authored 
      If the firmware had set up a clock to source from PLLC, go along with
it.  But if we're looking for a new parent, we don't want to switch it
to PLLC because the firmware will force PLLC (and thus the AXI bus
clock) to different frequencies during over-temp/under-voltage,
without notification to Linux.

On my system, this moves the Linux-enabled HDMI state machine and DSI1
escape clock over to plld_per from pllc_per.  EMMC still ends up on
pllc_per, because the firmware had set it up to use that.
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Fixes: 41691b88 ("clk: bcm2835: Add support for programming the audio domain clocks")
Acked-by: default avatarMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      67615c58
    • Eric Anholt's avatar
      clk: bcm2835: Mark the CM SDRAM clock's parent as critical · 9e400c5c
      Eric Anholt authored 
      While the SDRAM is being driven by its dedicated PLL most of the time,
there is a little loop running in the firmware that periodically turns
on the CM SDRAM clock (using its pre-initialized parent) and switches
SDRAM to using the CM clock to do PVT recalibration.

This avoids system hangs if we choose SDRAM's parent for some other
clock, then disable that clock.
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Acked-by: default avatarMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      9e400c5c
    • Eric Anholt's avatar
      clk: bcm2835: Mark GPIO clocks enabled at boot as critical · eddcbe83
      Eric Anholt authored 
      These divide off of PLLD_PER and are used for the ethernet and wifi
PHYs source PLLs.  Neither of them is currently represented by a phy
device that would grab the clock for us.

This keeps other drivers from killing the networking PHYs when they
disable their own clocks and trigger PLLD_PER's refcount going to 0.
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Acked-by: default avatarMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      eddcbe83
    • Eric Anholt's avatar
      clk: bcm2835: Mark the VPU clock as critical · e69fdcca
      Eric Anholt authored 
      The VPU clock is also the clock for our AXI bus, so we really can't
disable it.  This might have happened during boot if, for example,
uart1 (aux_uart clock) probed and was then disabled before the other
consumers of the VPU clock had probed.
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Acked-by: default avatarMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      e69fdcca
    • Stephen Boyd's avatar
      Merge tag 'v4.9-rockchip-clk1' of... · 9bb87c02
      Stephen Boyd authored 
      Merge tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk driver updates from Heiko Stuebner:

The biggest addition is probably the special clock-type for ddr clock
control. While reading that clock is done the normal way from the
registers, setting it always requires some sort of special handling
to let the system survive this addition.

As the commit message explains, there are currently 3 handling-types
known. General SRAM-based code on rk3288 and before (which is waiting
essentially for the PIE support that is currently being worked on),
SCPI-based clk setting on the rk3368 through a coprocessor, which we
might support once the support for legacy scpi-variants has matured
and now on the rk3399 (and probably later) using a dcf controller that
is controlled from the arm-trusted-firmware and gets accessed through
firmware calls from the kernel. This is the variant we currently
support, but the clock type is made to support the other variants in
the future as well.

Apart from that slightly bigger chunk, we have a mix of PLL rates,
clock-ids and flags mainly for the rk3399.

And interestingly an iomap fix for the legacy gate driver, where I
hopefully could deter the submitter from actually using that in any
new works.

* tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: use the dclk_vop_frac clock ids on rk3399
  clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers
  clk: rockchip: add 2016M to big cpu clk rate table on rk3399
  clk: rockchip: add rk3399 ddr clock support
  clk: rockchip: add dclk_vop_frac ids for rk3399 vop
  clk: rockchip: add new clock-type for the ddrclk
  soc: rockchip: add header for ddr rate SIP interface
  clk: rockchip: add SCLK_DDRC id for rk3399 ddrc
  clk: rockchip: handle of_iomap failures in legacy clock driver
  clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical
  clk: rockchip: use general clock flag when registering pll
  clk: rockchip: delete the CLK_IGNORE_UNUSED from aclk_pcie on rk3399
  clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI
      9bb87c02
    • Geert Uytterhoeven's avatar
      MAINTAINERS: Add section for Renesas clock drivers · fedc81e7
      Geert Uytterhoeven authored 
      Add a section for Renesas clock drivers, as found on Renesas ARM SoCs,
and list myself as the maintainer.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      fedc81e7
  3. 04 Sep, 2016 6 commits
  5. 03 Sep, 2016 1 commit
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  9. 01 Sep, 2016 2 commits
  11. 31 Aug, 2016 2 commits
  13. 30 Aug, 2016 5 commits
  15. 29 Aug, 2016 1 commit
  17. 26 Aug, 2016 2 commits
  19. 25 Aug, 2016 7 commits
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