- 26 Jul, 2010 9 commits
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Francisco Jerez authored
Init-compute-mem was the last piece missing for nv0x-nv3x card cold-booting. This implementation is somewhat lacking but it's been reported to work on most chipsets it was tested in. Let me know if it breaks suspend to RAM for you. Signed-off-by:
Francisco Jerez <currojerez@riseup.net> Tested-by:
Patrice Mandin <patmandin@gmail.com> Tested-by:
Ben Skeggs <bskeggs@redhat.com> Tested-by:
Xavier Chantry <chantry.xavier@gmail.com> Tested-by:
Marcin Kościelnicki <koriakin@0x04.net> Signed-off-by:
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Francisco Jerez authored
Also collect all the PFB registers in a single place and remove some duplicated definitions. Signed-off-by:
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Francisco Jerez authored
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Francisco Jerez authored
Rescaling interlaced modes isn't going to work correctly, and even if it did, come on, interlaced flat panels? are you pulling my leg? Signed-off-by:
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Francisco Jerez authored
It doesn't like variable length arrays. Signed-off-by:
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Ben Skeggs authored
A previous commit started additionally using the SOR link when trying to match the correct output script. However, we never fill in this field for LVDS so we can never match a script at all. Signed-off-by: -
Ben Skeggs authored
Based on a patch from Matthew Garrett. Signed-off-by:
Matthew Garrett <mjg@redhat.com>
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Ben Skeggs authored
There's a report of this quirk breaking modesetting on at least one board. After discussion with Francisco Jerez, we've decided to remove it: <darktama> it's not worth limiting the quirk to just where we know it can work? i'm happy either way really :) <curro> hmm, don't think so, most if not all DCB15 cards have just one DAC <curro> and with that quirk there's no way to tell if the load comes from the VGA or DVI port Signed-off-by: -
Ben Skeggs authored
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- 13 Jul, 2010 31 commits
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Francisco Jerez authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
On nv50 it became impossible to attempt a PCI ROM shadow of the VBIOS, which will break some setups. This patch also removes the different ordering of shadow methods for pre-nv50 chipsets. The reason for the different ordering was paranoia, but it should hopefully be OK to try shadowing PRAMIN first. Signed-off-by: -
Francisco Jerez authored
Fixes a lockup when coming back from suspend. Signed-off-by:
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Francisco Jerez authored
On older cards (<nv17) scanout gets blocked when the ROM is being accessed. PROM access usually comes out enabled from suspend, switch it off. Signed-off-by:
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Francisco Jerez authored
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Ben Skeggs authored
In some situations it's possible we can receive a spurious hotplug IRQ before we're ready to handle it, leading to an oops. Calling the display init before enabling interrupts should clear any pending IRQs on the GPU and prevent this from happening. Signed-off-by: -
Ben Skeggs authored
It seems on some chipsets that doing this from the 0x20 handler causes the display engine to not ever signal the final 0x40 stage. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Previously only done on nv50+ This commit also switches unknown NV2x/NV3x chipsets to noaccel mode. Signed-off-by: -
Ben Skeggs authored
This was always really a developer option, and if it's really necessary we can hack this in ourselves. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
This removes the previous prepare_access() and finish_access() hooks, and replaces it with a much simpler flush() hook. All the chipset-specific code before nv50 has its use removed completely, as it's not required there at all. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
Nouveau will no longer load at all if card initialisation fails, so all these checks are unnecessary. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
The previous handler basically worked correctly for a full-blown mode change. However, it did nothing at all when a partial (encoder only) reconfiguation was necessary, leading to the display hanging on certain types of mode switch. Signed-off-by: -
Ben Skeggs authored
It turns out that the display engine signals an interrupt for disconnects too. In order to make it easier to process the display interrupts correctly, we want to ensure we only get one operation per interrupt sequence - this is what this commit achieves. Signed-off-by: -
Francisco Jerez authored
The blob seems to have the same problem so it's probably a hardware issue (bug 28810). Signed-off-by:
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Francisco Jerez authored
Avoids an oops in the fence wait failure path (bug 26521). Signed-off-by:
Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by:
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Francisco Jerez authored
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Francisco Jerez authored
No need to spam the logs when they're found, they're equivalent to INIT_DONE. Signed-off-by:
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Francisco Jerez authored
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Francisco Jerez authored
Load detection needs the connector wired to a CRTC, when there are no inactive CRTCs left that means we need to cut some other head off for a while, causing intermittent flickering. Signed-off-by:
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