- 13 Jan, 2020 1 commit
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Rob Clark authored
Since zap firmware can be device specific, allow for a firmware-name property in the zap node to specify which firmware to load, similarly to the scheme used for dsp/wifi/etc. v2: only need a single error msg when we can't load from firmware-name specified path, and fix comment [Bjorn A.] Signed-off-by:Rob Clark <robdclark@chromium.org> Reviewed-by:
Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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- 12 Jan, 2020 2 commits
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Fritz Koenig authored
NV12 is a valid format for UBWC Signed-off-by:
Fritz Koenig <frkoenig@google.com> Signed-off-by:
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John Stultz authored
With the db845c running AOSP, I see the following error on every frame on the home screen: [drm:dpu_plane_atomic_check:915] [dpu error]plane33 invalid src 2880x1620+0+470 line:2560 This is due to the error paths in atomic_check using DPU_ERROR_PLANE(), and the drm_hwcomposer using atomic_check to decide how to composite the frame (thus it expects to see atomic_check to fail). In order to avoid spamming the logs, this patch converts the DPU_ERROR_PLANE() calls to DPU_DEBUG_PLANE() calls in atomic_check. Cc: Todd Kjos <tkjos@google.com> Cc: Alistair Delva <adelva@google.com> Cc: Amit Pundir <amit.pundir@linaro.org> Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <sean@poorly.run> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org Signed-off-by:
John Stultz <john.stultz@linaro.org> Signed-off-by:
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- 07 Jan, 2020 2 commits
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Harigovindan P authored
LANE_CTRL register in latest version of DSI controller (v2.2) has additional functionality introduced to enable/disable HS signalling with default value set to enabled. To accommodate this change, LANE_CTRL register should be read and bit wise ORed to enable non continuous clock mode. Without this change, if register is written directly, HS signalling will be disabled resulting in black screen. Changes in v1: -Update LANE_CTRL register value Changes in v2: -Changing commit message accordingly. Signed-off-by:
Harigovindan P <harigovi@codeaurora.org> Signed-off-by:
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Harigovindan P authored
Add support for v2.4.1 DSI block in the sc7180 SoC. Changes in v1: -Modify commit text to indicate DSI version and SOC detail(Jeffrey Hugo). -Splitting visionox panel driver code out into a different patch(set), since panel drivers are merged into drm-next via a different tree(Rob Clark). Changes in v2: -Update commit text accordingly(Matthias Kaehlcke). Signed-off-by:
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- 04 Jan, 2020 1 commit
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Rob Clark authored
Decouple enable and rate setting. Prep work to handle bootloader enabled display. Signed-off-by:
Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
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- 03 Jan, 2020 17 commits
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Wambui Karuga authored
As the if statement only checks for the value of the offset_name variable, it can be replaced by the more conscise BUG_ON macro for error reporting. Signed-off-by:
Wambui Karuga <wambui.karugax@gmail.com> Reviewed-by:
Sean Paul <sean@poorly.run> Signed-off-by:
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Fabio Estevam authored
Booting the adreno driver on a imx53 board leads to the following error message: adreno 30000000.gpu: [drm:adreno_gpu_init] *ERROR* Could not find the GPU powerlevels As the "qcom,gpu-pwrlevels" property is optional and never present on i.MX5, turn the message into debug level instead. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Reviewed-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c:2260:3-4: Unneeded semicolon Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
zhengbin <zhengbin13@huawei.com> Reviewed-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:741:2-3: Unneeded semicolon Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c:905:2-3: Unneeded semicolon Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/msm/hdmi/hdmi_connector.c:104:3-4: Unneeded semicolon Reported-by:
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Nathan Chancellor authored
Clang warns: ../drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c:124:3: warning: misleading indentation; statement is not part of the previous 'if' [-Wmisleading-indentation] mdp4_crtc_set_config(encoder->crtc, ^ ../drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c:121:2: note: previous statement is here if (mdp4_dsi_encoder->enabled) ^ This warning occurs because there is a space after the tab on this line. Remove it so that the indentation is consistent with the Linux kernel coding style and clang no longer warns. Fixes: 776638e7 ("drm/msm/dsi: Add a mdp4 encoder for DSI") Link: https://github.com/ClangBuiltLinux/linux/issues/792Signed-off-by:Nathan Chancellor <natechancellor@gmail.com> Reviewed-by:
Nick Desaulniers <ndesaulniers@google.com> Signed-off-by:
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Drew Davenport authored
The dpu_encoder_phys * argument passed to these functions will never be NULL so don't check. Signed-off-by:
Drew Davenport <ddavenport@chromium.org> Signed-off-by:
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Drew Davenport authored
The return statement follows another return statement, so will never be reached. Signed-off-by:
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Drew Davenport authored
dpu_encoder_virt.phys_encs[0:num_phys_encs-1] will not be NULL so don't check. Also fix multiline strings that caused checkpatch warning. Signed-off-by:
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Drew Davenport authored
dpu_crtc_mixer.hw_lm will never be NULL, so don't check. Signed-off-by:
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Drew Davenport authored
dpu_crtc_mixer.lm_ctl will never be NULL, so don't bother checking Signed-off-by:
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Drew Davenport authored
dpu_hw_ctl* is checked for NULL when passed as an argument to several functions. It will never be NULL, so remove the checks. Signed-off-by:
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Sharat Masetty authored
Add the relevant GBIF registers and the debug bus to the a6xx gpu state. This comes in pretty handy when debugging GPU bus related issues. Signed-off-by:
Sharat Masetty <smasetty@codeaurora.org> Signed-off-by:
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Sharat Masetty authored
This patch adds support for enabling Graphics Bus Interface(GBIF) used in multiple A6xx series chipets. Also makes changes to the PDC/RSC sequencing specifically required for A618. This is needed for proper interfacing with RPMH. Signed-off-by:
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Sharat Masetty authored
This patch adds Adreno 618 entry and its associated properties to the gpulist entries. Signed-off-by:
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Stephan Gerhold authored
At the moment, the MSM DSI driver calls drm_panel_enable() rather early from the DSI bridge pre_enable() function. At this point, the encoder (e.g. MDP5) is not enabled, so we have not started transmitting video data. However, the drm_panel_funcs documentation states that enable() should be called on the panel *after* video data is being transmitted: The .prepare() function is typically called before the display controller starts to transmit video data. [...] After the display controller has started transmitting video data, it's safe to call the .enable() function. This will typically enable the backlight to make the image on screen visible. Calling drm_panel_enable() too early causes problems for some panels: The TFT LCD panel used in the Samsung Galaxy Tab A 9.7 (2015) (APQ8016) uses the MIPI_DCS_SET_DISPLAY_BRIGHTNESS command to control backlight/brightness of the screen. The enable sequence is therefore: drm_panel_enable() drm_panel_funcs.enable(): backlight_enable() backlight_ops.update_status(): mipi_dsi_dcs_set_display_brightness(dsi, bl->props.brightness); The panel seems to silently ignore the MIPI_DCS_SET_DISPLAY_BRIGHTNESS command if it is sent too early. This prevents setting the initial brightness, causing the display to be enabled with minimum brightness instead. Adding various delays in the panel initialization code does not result in any difference. On the other hand, moving drm_panel_enable() to dsi_mgr_bridge_enable() fixes the problem, indicating that the panel requires the video stream to be active before the brightness command is accepted. Therefore: Move drm_panel_enable() to dsi_mgr_bridge_enable() to delay calling it until video data is being transmitted. Move drm_panel_disable() to dsi_mgr_bridge_disable() for similar reasons. (This is not strictly required for the panel affected above...) Tested-by:Jasper Korten <jja2000@gmail.com> Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Tested-by:
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- 02 Jan, 2020 16 commits
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Shubhashree Dhar authored
Fix max core clk rate during dt parsing in display driver. Signed-off-by:
Shubhashree Dhar <dhar@codeaurora.org> Signed-off-by:
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Shubhashree Dhar authored
Add scaler support for display driver. This patch has dependency on the below series https://patchwork.kernel.org/patch/11260267/Co-developed-by:
Raviteja Tamatam <travitej@codeaurora.org> Signed-off-by:
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Kalyan Thota authored
mixer selection in the display topology is based on multiple factors 1) mixers available in the hw 2) interfaces to be enabled 3) merge capability change will pickup mixer as per the topology need. Signed-off-by:
Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by:
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Kalyan Thota authored
Add changes to setup display datapath on SC7180 target. Changes in v1: - Add changes to support ctl_active on SC7180 target. - While selecting the number of mixers in the topology consider the interface width. Changes in v2: - Spawn topology mixer selection into separate patch (Rob Clark). - Add co-developed-by tags in the commit msg (Stephen Boyd). Changes in v3: - Fix kernel checkpatch errors in v2. This patch has dependency on the below series https://patchwork.kernel.org/patch/11253747/Co-developed-by:
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Kalyan Thota authored
Add display hw catalog changes for SC7180 target. Changes in v1: - Configure register offsets and capabilities for the display hw blocks. Changes in v2: - mdss_irq data type has changed in the dependent patch, accommodate the necessary changes. - Add co-developed-by tags in the commit msg (Stephen Boyd). Changes in v3: - fix kernel checkpatch errors in v2 Changes in v4: - move documentation into seperate patch (Rob Herring). This patch has dependency on the below series https://patchwork.kernel.org/patch/11253647/Co-developed-by:
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Kalyan Thota authored
Add a compatible string to support sc7180 dpu version. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Shubhashree Dhar authored
Current code assumes that all the irqs registers offsets can be accessed in all the hw revisions; this is not the case for some targets that should not access some of the irq registers. This change adds the support to selectively remove the irqs that are not supported in some of the hw revisions. Changes in v1: - Add support to selectively remove the hw irqs that are not not supported. Changes in v2: - Remove unrelated changes. Changes in v3: - Remove change-id (Stephen Boyd). - Add colon in variable description to match kernel-doc (Stephen Boyd). - Change macro-y way of variable description (Jordon Crouse). - Remove unnecessary if checks (Jordon Crouse). - Remove extra blank line (Jordon Crouse). Changes in v4: - Remove checkpatch errors. Signed-off-by:
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Fritz Koenig authored
Hardware only natively supports BGR8888 UBWC. UBWC support for RGB8888 can be had by pretending that the buffer is BGR. Signed-off-by:
Rob Clark <robdclark@gmail.com> Acked-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Stephen Boyd authored
These structures look like a bunch of data tables that aren't going to change after boot. Let's move them to the const RO section of memory so that they can't be modified at runtime on modern machines. Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Brian Masney authored
Set the two interconnect paths for the GPU to maximum speed for now to work towards getting the GPU working upstream. We can revisit a later time to optimize this for battery life. Signed-off-by:
Brian Masney <masneyb@onstation.org> Reviewed-by:
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Brian Masney authored
Set the two interconnect paths for the GPU to maximum speed for now to work towards getting the GPU working upstream. We can revisit a later time to optimize this for battery life. Signed-off-by:
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Brian Masney authored
Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core and must use the On Chip MEMory (OCMEM) in order to be functional. There's a separate interconnect path that needs to be setup to OCMEM. Add support for this second path to the GPU core. In the downstream MSM 3.4 sources, the two interconnect paths for the GPU are between: - MSM_BUS_MASTER_GRAPHICS_3D and MSM_BUS_SLAVE_EBI_CH0 - MSM_BUS_MASTER_V_OCMEM_GFX3D and MSM_BUS_SLAVE_OCMEM Signed-off-by:
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Brian Masney authored
Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core and must use the On Chip MEMory (OCMEM) in order to be functional. There's a separate interconnect path that needs to be setup to OCMEM. Let's document this second interconnect path that's available. Since there's now two available interconnects, let's add the interconnect-names property. Signed-off-by:
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Rob Clark authored
We can have two cases, when it comes to "zap" fw. Either the fw requires zap fw to take the GPU out of secure mode at boot, or it does not and we can write RBBM_SECVID_TRUST_CNTL directly. Previously we decided based on whether zap fw load succeeded, but this is not a great plan because: 1) we could have zap fw in the filesystem on a device where it is not required 2) we could have the inverse case Instead, shift to deciding based on whether we have a 'zap-shader' node in dt. In practice, there is only one device (currently) with upstream dt that does not use zap (cheza), and it already has a /delete-node/ for the zap-shader node. Fixes: abccb9fe ("drm/msm/a6xx: Add zap shader load") Signed-off-by:
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Rob Clark authored
Previously, if the freq were overriden (ie. via sysfs), it would get reset to max on resume. Signed-off-by:
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Rob Clark authored
This isn't an error. Also the clk APIs handle the NULL case, so we can just delete the check. Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Stephen Boyd <sboyd@kernel.org>
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- 29 Dec, 2019 1 commit
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Linus Torvalds authored
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