1. 12 Nov, 2012 3 commits
    • Archit Taneja's avatar
      OMAPDSS: DISPC: Use output width and height to calculate row/pix inc for writeback · 6be0d73e
      Archit Taneja authored
      When calculating row and pixel increments for graphics and video pipes, we need
      to consider the dimensions of the input frame to know how to read from the
      buffer. Hence, we need to calculate these parameters from the input to the
      pipeline.
      
      For writeback, the row and pixel increments need to be calculated based on the
      output of the writeback pipeline, i.e, the dimensions of the frame after
      scaling. Ensure that dispc driver uses values of out_width and out_height when
      calling calc_dma/calc_tiler_rotation_offset.
      
      For graphics and video pipes, the original code passed the original height as
      frame_height to calc_dma_rotation_offset, and not the predecimated height. This
      is left as it is for now. We need to figure out why pre decimated height isn't
      needed.
      Signed-off-by: default avatarArchit Taneja <archit@ti.com>
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      6be0d73e
    • Archit Taneja's avatar
      OMAPDSS: DISPC: Don't allow predecimation for writeback · 1c031441
      Archit Taneja authored
      Since writeback writes to a buffer instead of reading from one, predecimation
      doesn't make sense for it. Configure the width and height predecimation limits
      to 1 if the plane is writeback.
      Signed-off-by: default avatarArchit Taneja <archit@ti.com>
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      1c031441
    • Archit Taneja's avatar
      OMAPDSS: DISPC: Fix calc_scaling_44xx() bugs for writeback pipeline · 5d501085
      Archit Taneja authored
      dispc_ovl_calc_scaling_44xx() doesn't work correctly for writeback. There are
      two issues with it:
      
      - the function tries to calculate pixel clock for the input plane using
        dispc_plane_pclk_rate(), calling this with writeback as input plane results in
        a BUG(), this function shouldn't be called for writeback at all. Fix this by
        calculating pixel clock only when we are not in mem to mem mode.
      
      - the maximum input_width is the product of the downscale ratio supported and
        the and the given output_width. This was calculated incorrectly by dividing
        output_width with maxdownscale. Fix this.
      Signed-off-by: default avatarArchit Taneja <archit@ti.com>
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      5d501085
  2. 07 Nov, 2012 3 commits
  3. 06 Nov, 2012 9 commits
  4. 05 Nov, 2012 12 commits
    • Tomi Valkeinen's avatar
      OMAPDSS: DISPC: fix DS variable name · 230edc03
      Tomi Valkeinen authored
      check_horiz_timing_omap3() has a variable named 'DS'. i386 uses DS name
      for something else, causing a compilation error. As 'DS' is not a very
      good local variable name in the first place, let's change it to 'ds',
      fixing the issue.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      230edc03
    • Tomi Valkeinen's avatar
      Merge branch '3.8/dsi-pll-work' · a4ae0ba8
      Tomi Valkeinen authored
      Merge omapdss patches to enable using DSI PLL for DPI output.
      a4ae0ba8
    • Tomi Valkeinen's avatar
      OMAPDSS: DPI: always use DSI PLL if available · 0e8276ef
      Tomi Valkeinen authored
      We currently get the decision whether to use PRCM or DSI PLL clock for
      DPI from the board file. This is not a good way to handle it, and it
      won't work with device tree.
      
      This patch changes DPI to always use DSI PLL if it's available.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      0e8276ef
    • Tomi Valkeinen's avatar
      OMAPDSS: DPI: verify if DSI PLL is operational · 6061675b
      Tomi Valkeinen authored
      The SoCs that have DSI module should have a working DSI PLL. However,
      some rare boards have not connected the powers to the DSI PLL.
      
      This patch adds a function that tries to power up the DSI PLL, and
      reports if that doesn't succeed. DPI uses this function to fall back to
      PRCM clocks if DSI PLL doesn't work.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      6061675b
    • Tomi Valkeinen's avatar
      OMAPDSS: DPI: use dpi.dsidev to see whether to use dsi pll · 8a3db406
      Tomi Valkeinen authored
      Instead of using dpi_use_dsi_pll() to check if dsi pll is to be used, we
      can just check if dpi.dsidev != NULL.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      8a3db406
    • Tomi Valkeinen's avatar
      OMAPDSS: hide dss_select_dispc_clk_source() · a5b8399f
      Tomi Valkeinen authored
      dss.c currently exposes functions to configure the dispc source clock
      and lcd source clock. There are configured separately from the output
      drivers.
      
      However, there is no safe way for the output drivers to handle dispc
      clock, as it's shared between the outputs. Thus, if, say, the DSI driver
      sets up DSI PLL and configures both the dispc and lcd clock sources to
      that DSI PLL, the resulting dispc clock could be too low for, say, HDMI.
      
      Thus the output drivers should really only be concerned about the lcd
      clock, which is what the output drivers actually use. There's lot to do
      to clean up the dss clock handling, but this patch takes one step
      forward and removes the use of dss_select_dispc_clk_source() from the
      output drivers.
      
      After this patch, the output drivers only configure the lcd source
      clock. On omap4+ the dispc src clock is never changed from the default
      PRCM source. On omap3, where the dispc and lcd clocks are actually the
      same, setting the lcd clock source sets the dispc clock source.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      a5b8399f
    • Tomi Valkeinen's avatar
      OMAPDSS: setup default dss fck · 13a1a2b2
      Tomi Valkeinen authored
      We don't currently set the dss fck when starting up. This is not a
      problem, as we setup the fck later when configuring the pixel clocks. Or
      this is how it was for omap2, for the rest of the omaps this may not be
      so.
      
      For DSI, HDMI and also for DPI when using DSI PLL, we don't need to
      change the dss fck, and thus it may be left unconfigured. Usually the
      dss fck is already setup fine by default, but we can't trust this.
      
      This patch sets the dss fck to maximum at probe time.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      13a1a2b2
    • Tomi Valkeinen's avatar
      OMAPDSS: add dss_calc_clock_rates() back · 930b027e
      Tomi Valkeinen authored
      dss_calc_clock_rates() was removed earlier as it was not used, but it is
      needed for DSI PLL calculations, so this patch adds it back.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      930b027e
    • Tomi Valkeinen's avatar
      OMAPDSS: DSI: workaround for HSDiv problem · 7a98786c
      Tomi Valkeinen authored
      It looks like on many OMAP versions powers for both HSClk and HSDiv to
      be enabled to have a functional HSDiv.
      
      This patch fixes the issue by forcing both powers on.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      7a98786c
    • Tomi Valkeinen's avatar
      OMAPDSS: DSI: skip odd dividers when pck >= 100MHz · b7f1fe54
      Tomi Valkeinen authored
      The DSI PLL and HSDivider can be used to generate the pixel clock for
      LCD overlay manager, which then goes to DPI output. On the DPI output
      pin the voltage of the signal is shifted from the OMAP's internal
      minimal voltage to 1.8V range. The shifting is not instant, and the
      higher the clock frequency, the less time there is to shift the signal
      to nominal voltage.
      
      If the HSDivider's divider is greater than one and odd, the resulting
      pixel clock does not have 50% duty cycle. For example, with a divider of
      3, the duty cycle is 33%.
      
      When combining high frequency (in the area of 140MHz+) and non-50% duty
      cycle, it has been observed the the shifter does not have enough time to
      shift the voltage enough, and this leads to bad signal which is rejected
      by monitors.
      
      As a workaround this patch makes the divider calculation skip all odd
      dividers when the required pixel clock is over 100MHz. The limit of
      100MHz is a guesstimate.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      b7f1fe54
    • Tomi Valkeinen's avatar
      OMAPDSS: fix DPI & DSI init order · 046bc575
      Tomi Valkeinen authored
      DPI may use DSI PLL, so it depends on DSI. However, currently DPI driver
      is added first, which causes DPI initialization to fail when it tries to
      get the DSI PLL.
      
      This patch changes the init order to fix this.
      
      A better solution would be to separate DSI PLL and DSI drivers. They
      have dependencies, though, but we could still have DSI PLL as an
      independent entity that we could initialize before any of the output
      drivers.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      046bc575
    • Tomi Valkeinen's avatar
      Merge branch '3.8/misc-2' · 9296dbd7
      Tomi Valkeinen authored
      Merge omapdss miscellaneous patches.
      9296dbd7
  5. 29 Oct, 2012 13 commits
    • Tomi Valkeinen's avatar
      OMAPDSS: split hdmi muxing function · ffc81fc5
      Tomi Valkeinen authored
      Split the omap4_hdmi_mux_pads() function into two parts, one handles the
      tpd12s015 gpio muxing, the other handles the hdmi pins.
      
      This is clearer, as hdmi and tpd12s015 are separate devices, and it also
      allows us to mux those separately with DT.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Ricardo Neri <ricardo.neri@ti.com>
      Acked-by: default avatarTony Lindgren <tony@atomide.com>
      ffc81fc5
    • Tomi Valkeinen's avatar
      OMAPDSS: DISPC: remove dssdev depependency from error handler · b276dd09
      Tomi Valkeinen authored
      The dispc error handler tries to "fix" issues by disabling and enabling
      panel. This is problematic, as we're trying to remove the dependency
      from omapdss to the omap_dss_devices. It's also racy, and doesn't really
      fix anything.
      
      This patch removes the use of omap_dss_device from the error handler,
      and just disables and enables the associated overlay manager. This
      should produce similar results as the previous solution, without using
      dssdev.
      
      However, the error handling is still horrible. But the problem boils
      down to one question, to which I don't have a clear answer: what to do
      when a HW error happens?
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      b276dd09
    • Tomi Valkeinen's avatar
      OMAPDSS: DISPC: fix loop in error handler · 4c6c65b0
      Tomi Valkeinen authored
      The dispc's error handler has a loop inside another loop, and both use
      the same loop variable. This is clearly wrong, and this patch makes a
      new variable for the inner loop.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      4c6c65b0
    • Tomi Valkeinen's avatar
      OMAPDSS: fix DSI2 PLL clk names · 901e5fe5
      Tomi Valkeinen authored
      dss_generic_clk_source_names is missing the names for clocks from DSI2
      PLL. Add them.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      901e5fe5
    • Tomi Valkeinen's avatar
      OMAPFB: improve mode selection from EDID · 5e18e352
      Tomi Valkeinen authored
      The current omapfb code goes over all the modes found from the monitors
      EDID data, and searches for a mode that is compatible with the DSS
      hardware and has the highest x-res.
      
      While this works ok as such, it proves problematic when using DSI PLL
      for pixel clock. Calculating DSI PLL dividers is not the fastest of the
      operations, and while doing it for one mode is usually ok, doing it for
      20 modes is noticable.
      
      Also, the first mode given in the EDID data should be the native mode of
      the monitor, and thus also the best mode, so if that can be used, no
      need to look further.
      
      This patch changes the code to use the first mode that is compatible
      with the DSS hardware.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      5e18e352
    • Tomi Valkeinen's avatar
      OMAPFB: remove use of extended edid block · 2b5c0d4f
      Tomi Valkeinen authored
      It seems that using the second EDID block causes more problems than is
      of any help. The first mode in the extended block will get
      FB_MODE_IS_FIRST set, which will override the first mode from the first
      EDID block, thus making the default videomode selection not to work
      properly.
      
      This patch removes the use of the extended edid block for now.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      2b5c0d4f
    • Tomi Valkeinen's avatar
      OMAPDSS: HDMI: make hdmi pclk check more permissive · f236b892
      Tomi Valkeinen authored
      The hdmi driver tries to find the given video timings from its static
      list of timings, to find the required ID for the mode. The check tries
      to find exact match for the pixel clock, among other checks.
      
      with omapfb driver there can be some amount of error in the give pixel
      clock, as the pixel clock is converted between Hz and ps, thus the
      hdmi's check fails to find the mode.
      
      This patch makes the check more allowing, by rounding the pixel clocks
      to nearest MHz.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Ricardo Neri <ricardo.neri@ti.com>
      f236b892
    • Tomi Valkeinen's avatar
      OMAPDSS: HDMI: add 1920x1200 video mode · 7a7ce2c7
      Tomi Valkeinen authored
      Add 1920x1200 video mode to hdmi driver's static modelist.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Ricardo Neri <ricardo.neri@ti.com>
      7a7ce2c7
    • Tomi Valkeinen's avatar
      OMAPDSS: HDMI: use core power on/off with edid & detect · 4489823c
      Tomi Valkeinen authored
      This patch makes use of the hdmi_power_[on|off]_core() functions added
      in the previous patch. The functions are used when reading EDID or
      detecting if a monitor is connected.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Ricardo Neri <ricardo.neri@ti.com>
      4489823c
    • Tomi Valkeinen's avatar
      OMAPDSS: HDMI: split power_on/off to two parts · bb426fc9
      Tomi Valkeinen authored
      There's currently just one power-on function for HDMI, which enables the
      IP and the video output. When reading EDID or detecting if a monitor is
      connected, we don't need the video output.
      
      Enabling the video output for these operations is not a big problem in
      itself, but the quick enable/disable cycles caused by the operations
      seem to cause sync lost errors from time to time. Also, this makes it
      possible to read the EDID before the full video path has been set up.
      
      This patch splits the hdmi_power_on into two parts, hdmi_power_on_core
      and hdmi_power_on_full. The "full" version does what hdmi_power_on does
      currently, and hdmi_power_on_core only enables the core IP. Similar
      changes are made for power_off.
      
      Note that these don't allow the HDMI IP to be first enabled, and later
      enable the video output, but the HDMI IP will first need to be powered
      off before calling the full version. So this is rather limited
      implementation, but it fills the needs for reading EDID.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Ricardo Neri <ricardo.neri@ti.com>
      bb426fc9
    • Tomi Valkeinen's avatar
      OMAPDSS: DISPC: Add IRQ enable/status helpers · 4e0397cf
      Tomi Valkeinen authored
      DISPC irqs need to be handled from the compat layer and also in the
      future by the omapdrm. To make this possible, this patchs adds a set of
      helper functions, so that the irqs can be managed without direct
      register reads/writes.
      
      The following functions are added, and all the current direct reg
      reads/writes are changed to use these.
      
      u32 dispc_read_irqstatus(void);
      void dispc_clear_irqstatus(u32 mask);
      u32 dispc_read_irqenable(void);
      void dispc_write_irqenable(u32 mask);
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      4e0397cf
    • Tomi Valkeinen's avatar
      OMAPDSS: add dispc_ovl_enabled() · 04bd8ac1
      Tomi Valkeinen authored
      Add new dispc function, dispc_ovl_enabled(). This returns if the overlay
      enable bit is set in the registers.
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      04bd8ac1
    • Tomi Valkeinen's avatar
      OMAPDSS: DISPC: make _enable_mgr_out public as "dispc_mgr_enable" · f1a813d3
      Tomi Valkeinen authored
      We need a low level manager-enable function for omapdrm. We have that
      function as dispc internal func, _enable_mgr_out().
      
      This patch exposes that function, and renames it to dispc_mgr_enable().
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      f1a813d3