Although timeout has never been experienced, still to make it
meaningful, its better to return error if it ever occurs.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

As per databook, ACCEPT{U1,U2}ENA bits should be set after receiving
SetConfiguration Command.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

as per databook, these bits are cleared by hardware on each USB reset,
so no need to clear it explicitly by software in reset ISR.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

as per data book any HIRD threshold value greater than 4b1100 is
invalid. So set the maximum valid value as default values.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

set_halt for ep0 is called to stall a deferred control responses by the
gadget.  We already have a function to stall default control endpoint.
This patch points set_halt for ep0 to the already available function.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Michel Sanches <michel.sanches@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

In case we try to start an invalid test mode, we
will call dwc3_ep0_stall_and_restart() but we will
also call dwc3_ep0_out_start() which will start
a second transfer on ep0.

Let's prevent any problems by returning early in
the error case.
Signed-off-by: Felipe Balbi <balbi@ti.com>

whenever we want to stall ep0, we always call
dwc3_ep0_stall_and_restart() which makes sure
to send ep0state properly rendering the code
in __dwc3_gadget_ep_set_halt() duplicated.
Reported-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

resource_index is more human readable. No
functional changes.
Signed-off-by: Felipe Balbi <balbi@ti.com>

It makes it easier to read and also avoids
setting DWC3_EP_PENDING_REQUEST just so the
next branch evaluates true.

No functional changes otherwise.

Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Now we are sure that, if res_trans_idx is zero, then endpoint has been
stopped. So it's safe to just return if endpoint is already stopped. No
need to generate warning anymore.

While doing so, it's better to return when res_trans_idx is zero and
decrease one level of indentation.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>

[ balbi@ti.com: slightly changed commit log ]
Signed-off-by: Felipe Balbi <balbi@ti.com>

Synopsys specification clearly states under section "Device Power-On or
Soft Reset" that DCTL.CSftRst=1 should be first step.  So, just follow
what specification says.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Before taking core out of reset phy must be stable. So wait for 100ms
after clear phy reset.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

module.h header file was included twice.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>

In case of ep_disable and reset interrupt is received and, still there
was at least one request queued for dma transfer, then endpoint is
stopped first. Once endpoint is stopped, callback for all queued
request must be called.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

It is needed to enumerate recent cores like 2.10a.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

The definition of DWC3_DCTL_HIRD_THRES macro is
completely wrong. It will only work for when we
want to read the register's contents for that bitfield.

Change the macro so that it can be used to writing to
the register, and when we need to read, we can add
extra right shift of 24 bits.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>

[ balbi@ti.com: add a commit log ]
Signed-off-by: Felipe Balbi <balbi@ti.com>

By the time we're disabling the endpoint, HW
could already have posted more events to our
event buffer. In that case, we will receive
endpoint events for a disabled endpoint.

In order to protect ourselves from that situation,
we simply ignore endpoint interrupts whenever
the endpoint is disabled.
Tested-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

In case we get disconnected, we will call gadget
driver's disconnect method, which should make
sure to disable all endpoints. At that point
we will call stop_active_transfers() to make
sure we didn't leave any pending request on the
controller.
Tested-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

That IRQ is causing way too much trouble. We have
a different handling which was agreed with IP
provider and has been tested with FPGA and OMAP5.
Tested-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

We never set CMDIOC bit for Start Transfer
command, so that code will never be used.
Tested-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

If event status says that its last completed TRB but TRB is still owned
by HW then break from the loop, because we are not going to get correct
TRB status from trb control/size register.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

If an IN transfer is missed on isoc endpoint, then driver must insure
that next ep_queue is properly handled.
This patch fixes this issue by starting a new transfer for next queued
request.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

SOF Number is bit16:3 of DSTS. Correct the mask accordingly.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Correct  define for DWC3_TRB_SIZE_TRBSTS.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Currently in case of isoc, interrupt is programmed after each
TRB_NUM/4 ie 8th TRB. A TRB is programmed against each submitted
request from gadget. If we do not want to limit the minimum number of
necessary request to be submitted from gadget then we must receive
interrupt on each TRB submission. There can be such situation with a
gadget working with ping-pong buffer.

If a gadget does not want to receive interrupt after each request
completion then it may set no_interrupt flag.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

That's a much more intuitive name as that function
is only called at the completion of a Status Phase.

It also matches dwc3_ep0_complete_data() for
the completion of Data Phase.
Signed-off-by: Felipe Balbi <balbi@ti.com>

USB is always little endian, but this driver
could run on non little endian cpus. Let's
be carefull with that.
Signed-off-by: Felipe Balbi <balbi@ti.com>

There's no need for returning early. Instead,
we can call dwc3_ep0_stall_and_restart()
conditionally.
Signed-off-by: Felipe Balbi <balbi@ti.com>

According to the databook, the DWC3 Core will
reset those bits to 0 on USB Bus Reset. This
means we must re-enable those bits on every
reset interrupt.

Because we will always get a Reset interrupt
after loading a gadget driver, we can, instead
of re-enabling something that was just lost,
move the handling of those bits to the Reset
Interrupt.

This patch fixes USB30CV U1/U2 Test.
Signed-off-by: Gerard CAUVY <g-cauvy1@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

If we get a disconnect IRQ, we should take
the core out of low power mode so we can
reconnect afterwards.
Signed-off-by: Felipe Balbi <balbi@ti.com>

If we don't read out the contents of the register
(in order to reinitialize 'reg' variable) we will
be writing unknown contents to the DCTL register
whenever we try to use dwc3_gadget_wakeup() function.
Signed-off-by: Felipe Balbi <balbi@ti.com>

The same event buffers will be reused when coming
out of hibernation, so we must reinitialize them
properly to avoid any mistakes.

While at that, also take dwc3_event_buffers_setup()
out of __devinit section.
Signed-off-by: Felipe Balbi <balbi@ti.com>

Recent cores (>= 1.94a) have a set of new features,
commands and a slightly different programming model.

This patch aims to support those changes.
Signed-off-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

those two functions don't power PHYs, they simply
put them in suspend state. Rename to reflect better
what functions actually do.
Signed-off-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

retries is used twice without being reinitialized.
Signed-off-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds definitions for some new registers that have been
added to later versions of the controller, up to v2.10a.
Signed-off-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

That semicolon doesn't do anything, it's not
needed and should be removed.
Signed-off-by: Felipe Balbi <balbi@ti.com>

s/has/have. No functional changes, just
a typo fix on a code comment.
Signed-off-by: Felipe Balbi <balbi@ti.com>

On our Transfer Not Ready handlers, only
dwc3_ep0_do_control_status() had a different
list of parameters.

Align on the parameters in order to keep consistency.

No functional changes.
Signed-off-by: Felipe Balbi <balbi@ti.com>

IS_ALIGNED provides a much faster operation for
checking proper size alignment then a modulo
operation. Let's use it.
Reported-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>