- 01 Jul, 2020 40 commits
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Boyuan Zhang authored
To workaround an issue in DPG V2: update description. Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
James Zhu <james.zhu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Boyuan Zhang authored
Rename SOC15_DPG_MODE_OFFSET_2_0, RREG32_SOC15_DPG_MODE_2_0 and WREG32_SOC15_DPG_MODE_2_0 for VCN2.0, VCN2.5 and VCN3.0. These three macros are used VCN2.0, VCN2.5 and VCN3.0, therefore rename it to be a general name. Signed-off-by:
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Boyuan Zhang authored
Rename RREG32_SOC15_DPG_MODE and WREG32_SOC15_DPG_MODE for VCN1.0 These two macros are used specifically for VCN1.0, therefore rename it from general name to VCN1.0 specific name. Signed-off-by:
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Boyuan Zhang authored
Add range for vcn instance 1 for translation for internal register offset, which is needed for VCN3.0 V2: update description. Signed-off-by:
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Boyuan Zhang authored
Use indirect sram for secure DPG mode V2: update description. Signed-off-by:
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Boyuan Zhang authored
Add vcn_v3_0_pause_dpg_mode to pause/unpause DPG mode for VCN3.0 V2: update description. Signed-off-by:
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Boyuan Zhang authored
Add vcn_v3_0_stop_dpg_mode to power off in DPG mode for VCN3.0 V2: update description. Signed-off-by:
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Boyuan Zhang authored
Add vcn_v3_0_start_dpg_mode to setup and start VCN block in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by:
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Boyuan Zhang authored
Add vcn_v3_0_mc_resume_dpg_mode to resume memory controller in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by:
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Boyuan Zhang authored
Add vcn_v3_0_clock_gating_dpg_mode to enabling clock gating in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by:
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Likun Gao authored
Enable OUT OF BAND MONITER for sienna_cichlid. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Likun Gao authored
Enable RSMU SMN PG for sienna_cichlid. Signed-off-by:
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Likun Gao authored
Update golden setting for sienna_cichlid. Signed-off-by:
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Kenneth Feng authored
Bundle GPO with gfx DPM and enable it since gfxclk dpm should work first then GPO works. Signed-off-by:
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Kenneth Feng authored
GPO is graphics power optimizer. SMU calculates the 16 gfxclk V/F points according to the CU numbers and memory activity.RLC picks one of them according to the memory speed requirements for the data transmission. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Kenneth Feng authored
mmhub pg can be obvserved from PCTL_CTRL Signed-off-by:
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Kenneth Feng authored
enable athub pg and the status can be checked in ATHUB_MISC_CNTL. Signed-off-by:
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Le Ma authored
Statically allocated VM inv eng of gfxhub on sienna_cichlid is used up. Also VM inv eng is no need for mes ring. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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Le Ma authored
Pass a piece of memory to MES ucode to fill contents. Signed-off-by:
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Le Ma authored
Update for new member query_status_fence_gpu_mc_ptr in MESAPI_SET_HW_RESOURCES. Signed-off-by:
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Le Ma authored
Update mes_api_def.h to match the latest mes fw. v2: clean up coding style based on kernel standards: - fix indentation and alignment - break long lines - put the opening brace last on the line - remove unnecessary blank line and space - replace uint(32|64) with standard uint(32|64)_t Signed-off-by:
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Likun Gao authored
Add function to get pptable power limit for sienna_cichlid. Signed-off-by:
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Likun Gao authored
Enable APCC DFLL for sienna_cichlid. Signed-off-by:
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Likun Gao authored
Enable BACO for sienna_cichlid. Signed-off-by:
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shaoyunl authored
SMU firmware already been loaded from host, don't enable it for now. May need to re-work it if we want to enable the SMU for guest in the future. Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Signed-off-by:
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Likun Gao authored
Enable VCN dpm set for sienna_cichlid. Enable JPEG dpm set for sienna_cichlid. v2: squash in BACO fix (Kenneth) Signed-off-by:
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James Zhu authored
fix typo for vcn3/jpeg3 idle check Signed-off-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Likun Gao authored
Enable the feature of FCLK Deep Sleep for sienna_cichlid. Signed-off-by:
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Likun Gao authored
Enable the feature of Voltage Regulator (VR) Hot for sienna_cichlid. Signed-off-by:
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shaoyunl authored
amdkfd add support for sienna_cichlid virtual function Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Signed-off-by:
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Jay Cornwall authored
- Preserve scalar GPRs ttmp[4:11] and ttmp13 - Add single step exception during context save workaround - Remove incorrect PC adjustment during context save Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Reviewed-by:
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Jay Cornwall authored
The contents of macros are parsed by the assembler before conditions have been tested. This causes assembly errors when using IP-specific instructions in the IP-unified trap handler. Add a preprocessing step to filter IP-specific code. Also guard a Navi1x-specific instruction (no effect on Sienna_Cichlid). Signed-off-by:
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Jay Cornwall authored
- Replace SQC stores with TCP stores - Synchronize with MSG_SAVEWAVE via lgkmcnt - HW_REG_IB_STS is now read-only Signed-off-by:
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Yong Zhao authored
v4: drop get_tile_config, comment out other callbacks Signed-off-by:
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Jerry (Fangzhi) Zuo authored
Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Likun Gao authored
Only disable 3D pipe 1 on navi1x, enable 3D pipe 1 on Sienna_Cichlid. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Likun Gao authored
Each of HDP flush engine should be used by one ring, correct allocate of hdp flush engine to SDMA ring. Correct me value of each SDMA ring, as it was cleared when init microcode. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Likun Gao authored
Enable mmhub clockgating. Signed-off-by:
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Kenneth Feng authored
athub ls is bounded with hdp ls,verified. Signed-off-by:
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Kenneth Feng authored
IH cg verified Signed-off-by:
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