1. 28 Jun, 2016 6 commits
  2. 27 Jun, 2016 3 commits
  3. 24 Jun, 2016 29 commits
  4. 22 Jun, 2016 2 commits
    • Ville Syrjälä's avatar
      drm/i915: Refresh cached DP port register value on resume · 64989ca4
      Ville Syrjälä authored
      During hibernation the cached DP port register value will be left with
      whatever value we have there when we create the hibernation image.
      Currently that means the port (and eDP PLL) will be off in the cached
      value. However when we resume there is no guarantee that the value
      in the actual register will match the cached value. If i915 isn't
      loaded in the kernel that loads the hibernation image, the port may
      well be on (eg. left on by the BIOS). The encoder state readout
      does the right thing in this case and updates our encoder state
      to reflect the actual hardware state. However the post-resume modeset
      will then use the stale cached port register value in
      intel_dp_link_down() and potentially confuse the hardware.
      
      This was caught by the following assert
       WARNING: CPU: 3 PID: 5288 at ../drivers/gpu/drm/i915/intel_dp.c:2184 assert_edp_pll+0x99/0xa0 [i915]
       eDP PLL state assertion failure (expected on, current off)
      on account of the eDP PLL getting prematurely turned off when
      shutting down the port, since the DP_PLL_ENABLE bit wasn't set
      in the cached register value.
      
      Presumably I introduced this problem in
      commit 6fec7662 ("drm/i915: Use intel_dp->DP in eDP PLL setup")
      as before that we didn't update the cached value after shuttting the
      port down. That's assuming the port got enabled at least once prior
      to hibernating. If that didn't happen then the cached value would
      still have been totally out of sync with reality (eg. first boot w/o
      eDP on, then hibernate, and then resume with eDP on).
      
      So, let's fix this properly and refresh the cached register value from
      the hardware register during resume.
      
      DDI platforms shouldn't use the cached value during port disable at
      least, so shouldn't have this particular issue. They might still have
      issues if we skip the initial modeset and then try to retrain the link
      or something. But untangling this DP vs. DDI mess is a bigger topic,
      so let's jut punt on DDI for now.
      
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: stable@vger.kernel.org
      Fixes: 6fec7662 ("drm/i915: Use intel_dp->DP in eDP PLL setup")
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1463162036-27931-1-git-send-email-ville.syrjala@linux.intel.comReviewed-by: default avatarImre Deak <imre.deak@intel.com>
      64989ca4
    • Imre Deak's avatar
      drm/i915: Sanity check PPS HW state · de9c1b6b
      Imre Deak authored
      The wait for panel status helper will only function correctly if the
      HW panel timings are programmed correctly. Returning prematurely from
      this helper may lead to obscure bugs later, so sanity check the HW
      timing registers.
      
      v2:
      - Check the T8, T9 fields too, we do program them (Ville)
      
      CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1466096506-11937-1-git-send-email-imre.deak@intel.com
      de9c1b6b