- 21 Dec, 2011 23 commits
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Maxim Levitsky authored
Otherwice code that responsible for idling the card can't work. BIOS init tables are supposed to init the clocks to correct values, so that shouldn't cause any problems (we don't reclock by default anyway) Signed-off-by:
Maxim Levitsky <maximlevitsky@gmail.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Maxim Levitsky authored
Because doing polling while hardware is disabled is a bad idea... Signed-off-by:
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Maxim Levitsky authored
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Ben Skeggs authored
Exposes the same connector properties as the Radeon implementation, however their behaviour isn't exactly the same. The primary difference being that unless both hborder/vborder have been defined by the user, the driver will keep the aspect ratio of the overscanned area the same as the mode the display is programmed for. Enabled for digital outputs on GeForce 8 and up, excluding GF119. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
Prevents EVO getting all angry at us. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
A NV49 appeared a while back that was using the "nv41 style" pwm registers, rather than the "nv40 style" ones my board is using. This disproves the previous theory that the pwm controller choice is chipset-specific. So, after looking at a bunch of vbios images it appears that the next viable theory is that we should select the pwm controller to use based on the gpio line the fan is tied to, just like we do on nv50. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
The handling of the internal pwm fan controller is similar enough between current chipsets that it makes sense to share the logic, and bugfixes :) No hw backends converted yet, will automatically fall-through to the "old" per-chipset fanspeed hooks for now. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Martin Peres authored
Exposes the following sysfs entries: - fan0_input: read the rotational speed of the fan (poll a bit during 250ms) - pwm0: set the pwm duty cycle - pwm0_min/max: set the minimum/maximum pwm value v2 (Ben Skeggs): - nv50 pwm controller code removed in favour of other more complete code - FAN_RPM -> FAN_SENSE - merged FAN_SENSE readout into common code, not at all nv50-specific - protected fanspeed changes with perflvl_wr - formatting tidying - added some comments where things are shaky v3 (Martin Peres) - ensure duty min/max from thermal table are sane Signed-off-by:
Martin Peres <martin.peres@ensi-bourges.fr>
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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- 20 Dec, 2011 17 commits
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Ville Syrjälä authored
This function returns the number of planes used by a specific pixel format. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Rob Clark <rob.clark@linaro.org> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Rob Clark authored
Call connector->funcs->dpms(DPMS_ON) rather than just setting connector->dpms = DPMS_ON. This ensures that if the connector has something to do to enable the output (rather than just using drm_helper_connector_dpms helper directly), that this happens at bootup. This solves an issue with connectors not getting enabled from fbcon_init() when the driver is loaded. Signed-off-by:
Rob Clark <rob@ti.com> Reviewed-by:
Adam Jackson <ajax@redhat.com> Signed-off-by:
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Dave Airlie authored
If the bpc is set from the connector is 0, we then use it later to adjust in a special case the HDMI pixel clock, however if the bpc is 0, we end up passing a 0 pixel clock into the code. I'm not sure if this is the correct answer or if we should avoid the HDMI clock adjustment for 0 values. This fixes a divide by 0 on my Llano system with a HDMI monitor and hdmi audio enabled. Reviewed-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
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Dave Airlie authored
* 'drm-radeon-next' of ../drm-radeon-next: drm/radeon: introduce a sub allocator and convert ib pool to it v4 drm/radeon/kms: add support for per-ring fence interrupts drm/radeon/kms: add cayman specific fence_ring_emit drm/radeon/kms: add some new ring params to better handle other ring types drm/radeon: improve radeon_test_syncing function drm/radeon: precompute fence cpu/gpu addr once v3 drm/radeon: move ring debugfs into radeon_ring.c drm/radeon: rename struct radeon_cp to radeon_ring drm/radeon: disable compute rings on cayman for now drm/radeon: add radeon_fence_count_emited function drm/radeon: make some asic pointers per ring drm/radeon: Add radeon_test_syncing function v2 drm/radeon: make cp variable an array drm/radeon: make ring rptr and wptr register offsets variable drm/radeon: make all functions work with multiple rings. drm/radeon/kms: add support for semaphores v3 drm/radeon/kms: add support for multiple fence queues v2 drm/radeon: fix a spelling mistake drm/radeon: no need to check all relocs for duplicates drm/radeon: fix debugfs handling v3
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Jerome Glisse authored
Somewhat specializaed sub-allocator designed to perform sub-allocation for command buffer not only for current cs ioctl but for future command submission ioctl as well. Patch also convert current ib pool to use the sub allocator. Idea is that ib poll buffer can be share with other command buffer submission not having 64K granularity. v2 Harmonize pool handling and add suspend/resume callback to pin/unpin sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman, rs480, rs690, rs880) v3 Simplify allocator v4 Fix radeon_ib_get error path to properly free fence Signed-off-by:
Jerome Glisse <jglisse@redhat.com> Signed-off-by:
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Alex Deucher authored
Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Christian König <deathsimple@vodafone.de> Signed-off-by:
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Alex Deucher authored
cayman is wb only and doesn't have a VC. Signed-off-by:
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Alex Deucher authored
Some rptr/wptrs fields have different offsets and not all rings are pm4 so add a new nop field. Signed-off-by:
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Christian König authored
Also test multiple waits on the same semaphore. Signed-off-by:
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Jerome Glisse authored
Add a start fence driver helper function which will be call once for each ring and will compute cpu/gpu addr for fence depending on wether to use wb buffer or scratch reg. This patch replace initialize fence driver separately which was broken in regard of GPU lockup. The fence list for created, emited, signaled must be initialize once and only from the asic init callback not from the startup call back which is call from the gpu reset. v2: With this in place we no longer need to know the number of rings in fence_driver_init, also writing to the scratch reg before knowing its offset is a bad idea. v3: rebase on top of change to previous patch in the serie Signed-off-by: -
Christian König authored
Those debugfs files aren't r600 specific, so they shouldn't be in r600.c. Move them to radeon_ring.c and also add functionality to dump CP1 & CP2 ring informations. Signed-off-by:
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Christian König authored
That naming seems to make more sense, since we not only want to run PM4 rings with it. Signed-off-by:
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Christian König authored
Disable the additional compute rings on cayman until their setup is fully implemented. Signed-off-by:
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Christian König authored
Split counting of emited fences out of power management into a seperate function. Signed-off-by:
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Christian König authored
Emitting fences, semaphores and ib works differently on different ring, so its is easier to maintain separate functions for each ring. Signed-off-by:
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Christian König authored
Tests syncing between all rings by using semaphores and fences. v2: use radeon_testing as a bit flag rather than on/off switch this allow to test for one thing at a time (bo_move or semaphore test). It kind of break the usage if user wheren't using 1 for bo move test but as it's a test feature i believe it's ok. Signed-off-by: -
Christian König authored
Replace cp, cp1 and cp2 members with just an array of radeon_cp structs. Signed-off-by:
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