- 14 Jul, 2016 40 commits
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Ben Skeggs authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
GP100 still supports the previous generations' page table layout, which we will temporarily make use of here. Proper support for the new MMU layout requires some rework to the common MMU code, which is in progress. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Just enough to get at the PLL table. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
GFxxx/GM1xx support the selection of 64/128KiB big pages globally. GM2xx supports the same, as well as another mode where the page size can be selected per-instance. We default to 128KiB pages (With per-instance for GM200, but the current code selects 128KiB there already) as the MMU code isn't currently able to handle otherwise. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
Fixes the second DVI output on Quadro FX380. Thanks to NVIDIA for providing the details on the full workaround. Signed-off-by: -
Ben Skeggs authored
Makes common the code that was previously used by the PMU table parsing, as it appears other tables need this too. Not much of an idea what this is all about... Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Some VBIOS have separate tables for each link of a given output path, which means we have to specify the specific link we're using instead of all possible links. Signed-off-by: -
Ben Skeggs authored
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Julia Lawall authored
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Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Roy Spliet authored
v2: fix typo it's -> its Signed-off-by:
Roy Spliet <nouveau@spliet.org> Signed-off-by:
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Roy Spliet authored
Corresponds with GT215. Don't rely on the lock test logic being unconditionally enabled, and disable test logic when done (presumably to save power). v2: Remove warning, nvkm_msec already warns on time-out Signed-off-by:
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Alexandre Courbot authored
Defer the loading of firmware files to the chip-specific part of secure boot. This allows implementations to retry loading firmware if the first attempt failed ; for the GM200 implementation, this happens when trying to reset a falcon, typically in reaction to GR init. Firmware loading may fail for a variety of reasons, such as the filesystem where they reside not being ready at init time. This new behavior allows GR to be initialized the next time we try to use it if the firmware has become available. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
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Alexandre Courbot authored
Make it possible to call gm20x_secboot_prepare_blobs() several times after either success or failure without re-building already existing blobs. The function will now try to load firmware files that have previously failed before returning success. Signed-off-by:
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Alexandre Courbot authored
Handle and propagate secure boot errors. Failure to do so results in Nouveau incorrectly believing init has succeeded and a completely black display during boot. If we propagate the error, GR init will fail and the user will at least have a working display. Signed-off-by:
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Alexandre Courbot authored
Some members were documented in the wrong structure. Signed-off-by:
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Karol Herbst authored
it is a little help for hardware monitoring tools Signed-off-by:
Karol Herbst <karolherbst@gmail.de> Signed-off-by:
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Karol Herbst authored
We shouldn't set voltages below the min or above the max voltage the gpu is able to set, so save the range for future lookups. Signed-off-by:
Martin Peres <martin.peres@free.fr> Tested-by:
Pierre Moreau <pierre.morrow@free.fr> Signed-off-by:
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Alexandre Courbot authored
This patch adds support for advanced features supported by the Noise-Aware PLL of Maxwell. Glitchless switch allows the PL field to be updated without disabling the PLL first if the SYNC_MODE bit of the CFG register is set. More significantly, DFS allows the PLL to monitor the actual input voltage and to dynamically lower the output frequency accordingly. This allows the clock to be more tolerant of lower voltages. These improvements are only supported for Tegra speedos >= 1. Also add the voltage table that is suitable for GM20B's NAPLL. This change needs to be done atomically for the right voltages to be used by the clock driver. v2. Fix build on non-Tegra platforms Signed-off-by:
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Alexandre Courbot authored
Strip the _ prefix off the gk20a clock constructor. Signed-off-by:
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Alexandre Courbot authored
Split the MNP programming function into two functions for the cases where we allow sliding or not, instead of making it take a parameter for this. This results in less conditionals in the code and makes it easier to read. Also make the MNP programming functions take the PLL parameters as arguments, and move bits of code to more relevant places (previous programming tended to be just-in-time, which added more conditionnals in the code). Signed-off-by:
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Alexandre Courbot authored
Use a dedicated function instead of always calculating n_lo on the fly. Signed-off-by:
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Alexandre Courbot authored
Make functions manipulating PLL settings take them as an argument, instead of assuming we want to work on the copy in the gk20a_clk structure. This makes these functions more flexible, which we will need in GM20B. Signed-off-by:
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Alexandre Courbot authored
Add relevant functions to work with the gk20a_pll structure and use them where they ought to be instead of directly manipulating registers. Signed-off-by:
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Alexandre Courbot authored
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