1. 08 Dec, 2017 3 commits
    • Daniel Vetter's avatar
      intel/atomic: Stop updating legacy fb parameters · 7a1530d7
      Daniel Vetter authored
      Even fbc isn't using this stuff anymore, so time to remove it.
      
      Cleaning up one small piece of the atomic conversion cruft at the time
      ...
      
      Quick explanation on why the plane->fb assignment is ok to delete: The
      core code takes care of the refcounting and legacy ->fb pointer
      updating, but drivers are allowed to update it ahead of time. Most
      legacy modeset drivers did that as part of their set_config callback
      (since that's how the legacy/crtc helpers worked). In i915 we only
      need that to make the fbc code happy.
      
      v2: don't nuke the assignement of intel_crtc->config, I accidentally
      set CI ablaze :-) Spotted by Maarten. And better explain why nuking
      the ->fb assignement shouldn't set off alarm bells.
      
      Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20171207143202.6021-1-daniel.vetter@ffwll.ch
      7a1530d7
    • Tvrtko Ursulin's avatar
      drm/i915: Restore GT performance in headless mode with DMC loaded · b6876374
      Tvrtko Ursulin authored
      It seems that the DMC likes to transition between the DC states a lot when
      there are no connected displays (no active power domains) during command
      submission.
      
      This activity on DC states has a negative impact on the performance of the
      chip with huge latencies observed in the interrupt handlers and elsewhere.
      Simple tests like igt/gem_latency -n 0 are slowed down by a factor of
      eight.
      
      Work around it by introducing a new power domain named,
      POWER_DOMAIN_GT_IRQ, associtated with the "DC off" power well, which is
      held for the duration of command submission activity.
      
      CNL has the same problem which will be addressed as a follow-up. Doing
      that requires a fix for a DC6 context corruption problem in the CNL DMC
      firmware which is yet to be released.
      
      v2:
       * Add commit text as comment in i915_gem_mark_busy. (Chris Wilson)
       * Protect macro body with braces. (Jani Nikula)
      
      v3:
       * Add dedicated power domain for clarity. (Chris, Imre)
       * Commit message and comment text updates.
       * Apply to all big-core GEN9 parts apart for Skylake which is pending DMC
         firmware release.
      
      v4:
       * Power domain should be inner to device runtime pm. (Chris)
       * Simplify NEEDS_CSR_GT_PERF_WA macro. (Chris)
       * Handle async DMC loading by moving the GT_IRQ power domain logic into
         intel_runtime_pm. (Daniel, Chris)
       * Include small core GEN9 as well. (Imre)
      
      v5
       * Special handling for async DMC load is not needed since on failure the
         power domain reference is kept permanently taken. (Imre)
      
      v6:
       * Drop the NEEDS_CSR_GT_PERF_WA macro since all firmwares have now been
         deployed. (Imre, Chris)
      Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100572
      Testcase: igt/gem_exec_nop/headless
      Cc: Imre Deak <imre.deak@intel.com>
      Acked-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
      Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v5)
      Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      [Imre: Add note about applying the WA on CNL as a follow-up]
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20171205132854.26380-1-tvrtko.ursulin@linux.intel.com
      b6876374
    • Chris Wilson's avatar
      drm/i915/execlists: Cache ELSP register offset · 2fc7a06a
      Chris Wilson authored
      Currently on every submission, we recalculate the ELSP register offset
      for the engine, after chasing the pointers to find the iomem base. Since
      this is fixed for the lifetime of the driver, record the offset in the
      execlists struct.
      
      In practice the difference is negligible, it just happens to remove 27
      bytes of eyesore pointer dancing from next to the hottest instruction
      (which is itself due to stalling for a cache miss) in perf profiles of
      the execlists_submission_tasklet().
      
      v2: Trim off one more elsp local.
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
      Reviewed-by: default avatarMichel Thierry <michel.thierry@intel.com>
      Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20171207222434.17686-1-chris@chris-wilson.co.uk
      2fc7a06a
  2. 07 Dec, 2017 3 commits
  3. 06 Dec, 2017 8 commits
  4. 05 Dec, 2017 5 commits
  5. 04 Dec, 2017 15 commits
    • Lionel Landwerlin's avatar
      drm/i915/cnl: only divide up base frequency with crystal source · 53ff2641
      Lionel Landwerlin authored
      We apply this logic to Gen9 as well. We didn't notice this issue as
      most part we've encountered so far only use the crystal as source for
      their timestamp registers.
      
      Fixes: dab91783 ("drm/i915: expose command stream timestamp frequency to userspace")
      Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20171113233455.12085-5-lionel.g.landwerlin@intel.com
      53ff2641
    • Randy Dunlap's avatar
      documentation/gpu/i915: fix docs build error after file rename · 006c2332
      Randy Dunlap authored
      Fix documentation build errors after intel_guc_loader.c was
      renamed to intel_guc_fw.c.
      
      Error: Cannot open file ../drivers/gpu/drm/i915/intel_guc_loader.c
      WARNING: kernel-doc '../scripts/kernel-doc -rst -enable-lineno -function GuC-specific firmware loader ../drivers/gpu/drm/i915/intel_guc_loader.c' failed with return code 1
      Error: Cannot open file ../drivers/gpu/drm/i915/intel_guc_loader.c
      Error: Cannot open file ../drivers/gpu/drm/i915/intel_guc_loader.c
      WARNING: kernel-doc '../scripts/kernel-doc -rst -enable-lineno -internal ../drivers/gpu/drm/i915/intel_guc_loader.c' failed with return code 2
      
      Fixes: e8668bbc ("drm/i915/guc: Rename intel_guc_loader.c to
      	intel_guc_fw.c")
      Signed-off-by: default avatarRandy Dunlap <rdunlap@infradead.org>
      Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      Link: https://patchwork.freedesktop.org/patch/msgid/1b214f53-47f5-bef3-f58e-8136de5678ed@infradead.org
      006c2332
    • Zhenyu Wang's avatar
      drm/i915/gvt: set max priority for gvt context · 1603660b
      Zhenyu Wang authored
      This is to workaround guest driver hang regression after
      preemption enable that gvt hasn't enabled handling of that
      for guest workload. So in effect this disables preemption
      for gvt context now.
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      1603660b
    • Zhenyu Wang's avatar
      drm/i915/gvt: Don't mark vgpu context as inactive when preempted · da5f99ea
      Zhenyu Wang authored
      We shouldn't mark inactive for vGPU context if preempted,
      which would still be re-scheduled later. So keep active state.
      
      Fixes: d6c05113 ("drm/i915/execlists: Distinguish the incomplete context notifies")
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      da5f99ea
    • Changbin Du's avatar
      drm/i915/gvt: Kick scheduler when new workload queued · c130456c
      Changbin Du authored
      The current schedule policy rely on a 1ms timer to execute workload. This
      can introduce maximum 1ms unnecessary latency. This is especially bad for
      small media workloads.
      
      And I don't think we need this timer for QoS, but the change is not simply
      remove the code. So I made a new API intel_gvt_kick_schedule() for future
      change.
      Signed-off-by: default avatarChangbin Du <changbin.du@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      c130456c
    • Changbin Du's avatar
      drm/i915/gvt: Convert macro queue_workload to a function · 59a716c6
      Changbin Du authored
      Convert the macro to a function which should always be preferred.
      Signed-off-by: default avatarChangbin Du <changbin.du@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      59a716c6
    • Tina Zhang's avatar
      drm/i915/gvt: Free dmabuf_obj list in intel_vgpu_dmabuf_cleanup · 82a3b670
      Tina Zhang authored
      The per vGPU dmabuf_obj list should be released in intel_vgpu_dmabuf_
      cleanup, which is invoked either in the process of closing a VM or in
      the process of removing a vGPU.
      
      Fixes: e3a0d7976c53 ("drm/i915/gvt: Handle orphan dmabuf_objs")
      Signed-off-by: default avatarTina Zhang <tina.zhang@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      82a3b670
    • Tina Zhang's avatar
      drm/i915/gvt: Introduce KBL to dma-buf on Gvt-g · 4a136d59
      Tina Zhang authored
      This patch introduces KBL platform to dma-buf on Gvt-g.
      Signed-off-by: default avatarTina Zhang <tina.zhang@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      4a136d59
    • Tina Zhang's avatar
      drm/i915/gvt: Handle orphan dmabuf_objs · dfb6ae4e
      Tina Zhang authored
      dmabuf_obj's destruction relys on GEM release operation, which is managed
      in i915 driver. And there is a time window between vgpu's destruction and
      its dmabuf_objs' destruction. This patch is to free the orphan dmabuf_objs
      correctly after the vgpu passes away.
      Signed-off-by: default avatarTina Zhang <tina.zhang@intel.com>
      Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      dfb6ae4e
    • Tina Zhang's avatar
      drm/i915/gvt: Dmabuf support for GVT-g · e546e281
      Tina Zhang authored
      This patch introduces a guest's framebuffer sharing mechanism based on
      dma-buf subsystem. With this sharing mechanism, guest's framebuffer can
      be shared between guest VM and host.
      
      v17:
      - modify VFIO_DEVICE_GET_GFX_DMABUF interface. (Alex)
      
      v16:
      - add x_hot and y_hot. (Gerd)
      - add flag validation for VFIO_DEVICE_GET_GFX_DMABUF. (Alex)
      - rebase 4.14.0-rc6.
      
      v15:
      - add VFIO_DEVICE_GET_GFX_DMABUF ABI. (Gerd)
      - add intel_vgpu_dmabuf_cleanup() to clean up the vGPU's dmabuf. (Gerd)
      
      v14:
      - add PROBE, DMABUF and REGION flags. (Alex)
      
      v12:
      - refine the lifecycle of dmabuf.
      
      v9:
      - remove dma-buf management. (Alex)
      - track the dma-buf create and release in kernel mode. (Gerd) (Daniel)
      
      v8:
      - refine the dma-buf ioctl definition.(Alex)
      - add a lock to protect the dmabuf list. (Alex)
      
      v7:
      - release dma-buf related allocations in dma-buf's associated release
        function. (Alex)
      - refine ioctl interface for querying plane info or create dma-buf.
        (Alex)
      
      v6:
      - align the dma-buf life cycle with the vfio device. (Alex)
      - add the dma-buf related operations in a separate patch. (Gerd)
      - i915 related changes. (Chris)
      
      v5:
      - fix bug while checking whether the gem obj is gvt's dma-buf when user
        change caching mode or domains. Add a helper function to do it.
        (Xiaoguang)
      - add definition for the query plane and create dma-buf. (Xiaoguang)
      
      v4:
      - fix bug while checking whether the gem obj is gvt's dma-buf when set
        caching mode or doamins. (Xiaoguang)
      
      v3:
      - declare a new flag I915_GEM_OBJECT_IS_GVT_DMABUF in drm_i915_gem_object
        to represent the gem obj for gvt's dma-buf. The tiling mode, caching
        mode and domains can not be changed for this kind of gem object. (Alex)
      - change dma-buf related information to be more generic. So other vendor
        can use the same interface. (Alex)
      
      v2:
      - create a management fd for dma-buf operations. (Alex)
      - alloc gem object's backing storage in gem obj's get_pages() callback.
        (Chris)
      Signed-off-by: default avatarTina Zhang <tina.zhang@intel.com>
      Cc: Alex Williamson <alex.williamson@redhat.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Gerd Hoffmann <kraxel@redhat.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      e546e281
    • Tina Zhang's avatar
      vfio: ABI for mdev display dma-buf operation · e20eaa23
      Tina Zhang authored
      Add VFIO_DEVICE_QUERY_GFX_PLANE ioctl command to let user query and get
      a plane and its information. So far, two types of buffers are supported:
      buffers based on dma-buf and buffers based on region.
      
      This ioctl can be invoked with:
      1) Either DMABUF or REGION flag. Vendor driver returns a plane_info
      successfully only when the specific kind of buffer is supported.
      2) Flag PROBE. And at the same time either DMABUF or REGION must be set,
      so that vendor driver returns success only when the specific kind of
      buffer is supported.
      
      Add VFIO_DEVICE_GET_GFX_DMABUF ioctl command to let user get a specific
      dma-buf fd of an exposed MDEV buffer provided by dmabuf_id which was
      returned in VFIO_DEVICE_QUERY_GFX_PLANE ioctl command.
      
      The life cycle of an exposed MDEV buffer is handled by userspace and
      tracked by kernel space. The returned dmabuf_id in struct vfio_device_
      query_gfx_plane can be a new id of a new exposed buffer or an old id of
      a re-exported buffer. Host user can check the value of dmabuf_id to see
      if it needs to create new resources according to the new exposed buffer
      or just re-use the existing resource related to the old buffer.
      
      v18:
      - update comments for VFIO_DEVICE_GET_GFX_DMABUF. (Alex)
      
      v17:
      - modify VFIO_DEVICE_GET_GFX_DMABUF interface. (Alex)
      
      v16:
      - add x_hot and y_hot fields. (Gerd)
      - add comments for VFIO_DEVICE_GET_GFX_DMABUF. (Alex)
      - rebase to 4.14.0-rc6.
      
      v15:
      - add a ioctl to get a dmabuf for a given dmabuf id. (Gerd)
      
      v14:
      - add PROBE, DMABUF and REGION flags. (Alex)
      
      v12:
      - add drm_format_mod back. (Gerd and Zhenyu)
      - add region_index. (Gerd)
      
      v11:
      - rename plane_type to drm_plane_type. (Gerd)
      - move fields of vfio_device_query_gfx_plane to vfio_device_gfx_plane_info.
        (Gerd)
      - remove drm_format_mod, start fields. (Daniel)
      - remove plane_id.
      
      v10:
      - refine the ABI API VFIO_DEVICE_QUERY_GFX_PLANE. (Alex) (Gerd)
      
      v3:
      - add a field gvt_plane_info in the drm_i915_gem_obj structure to save
        the decoded plane information to avoid look up while need the plane
        info. (Gerd)
      Signed-off-by: default avatarTina Zhang <tina.zhang@intel.com>
      Reviewed-by: default avatarGerd Hoffmann <kraxel@redhat.com>
      Reviewed-by: default avatarKirti Wankhede <kwankhede@nvidia.com>
      Acked-by: default avatarAlex Williamson <alex.williamson@redhat.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      e20eaa23
    • Tina Zhang's avatar
      drm/i915/gvt: Add framebuffer decoder support · 9f31d106
      Tina Zhang authored
      This patch is to introduce the framebuffer decoder which can decode guest
      OS's framebuffer information, including primary, cursor and sprite plane.
      
      v16:
      - rebase to 4.14.0-rc6.
      
      v14:
      - refine pixel format table. (Zhenyu)
      
      v9:
      - move drm format change to a separate patch. (Xiaoguang)
      
      v8:
      - fix a bug in decoding primary plane. (Tina)
      
      v7:
      - refine framebuffer decoder code. (Zhenyu)
      Signed-off-by: default avatarTina Zhang <tina.zhang@intel.com>
      Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      9f31d106
    • Tina Zhang's avatar
      drm/i915/gvt: Add opregion support · b851adea
      Tina Zhang authored
      Windows guest driver needs vbt in opregion, to configure the setting
      for display. Without opregion support, the display registers won't
      be set and this blocks display model to get the correct information
      of the guest display plane.
      
      This patch is to provide a virtual opregion for guest. The original
      author of this patch is Xiaoguang Chen.
      
      This patch is split from the "Dma-buf support for GVT-g" patch set,
      with being rebased to the latest gvt-staging branch.
      
      v3:
      - add checking region index during intel_vgpu_rw. (Xiong)
      
      v2:
      - refine intel_vgpu_reg_release_opregion. (Xiong)
      
      Here are the previous version comments:
      
      v18:
      - unmap vgpu's opregion when destroying vgpu.
      
      v16:
      - rebase to 4.14.0-rc6.
      Signed-off-by: default avatarBing Niu <bing.niu@intel.com>
      Signed-off-by: default avatarTina Zhang <tina.zhang@intel.com>
      Tested-by: default avatarXiong Zhang <xiong.y.zhang@intel.com>
      Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      b851adea
    • Xiong Zhang's avatar
      drm/i915/gvt: Alloc and Init guest opregion at vgpu creation · 4dff110b
      Xiong Zhang authored
      Currently guest opregion is allocated and initialised when guest
      write opregion base register. This is too late for kvmgt, so
      move it to vgpu_create time.
      Signed-off-by: default avatarXiong Zhang <xiong.y.zhang@intel.com>
      Tested-by: default avatarTina Zhang <tina.zhang@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      4dff110b
    • Chris Wilson's avatar
      drm/i915/gvt: Fix out-of-bounds buffer write into opregion->signature[] · ea26c96d
      Chris Wilson authored
      sparse spots
      
      drivers/gpu/drm/i915/gvt/opregion.c:234 alloc_and_init_virt_opregion() error: memcpy() 'header->signature' too small (16 vs 17)
      
      as gvt is indeed trying to memcpy a string longer than the signature[].
      
      Fixes: b2d6ef70 ("drm/i915/gvt: Let each vgpu has separate opregion memory")
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Xiong Zhang <xiong.y.zhang@intel.com>
      Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
      Cc: Zhi Wang <zhi.a.wang@intel.com>
      Cc: intel-gvt-dev@lists.freedesktop.org
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      ea26c96d
  6. 02 Dec, 2017 1 commit
  7. 01 Dec, 2017 5 commits