- 19 Jan, 2018 19 commits
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Oscar Mateo authored
Instead of returning whatever size the latest GEN used. This is because context sizes for new GENs can go up or down, but the only safe thing to do for missing cases is to use the largest known one, whatever that is. Suggested-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:
Oscar Mateo <oscar.mateo@intel.com> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1515711307-28979-1-git-send-email-oscar.mateo@intel.com
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Tvrtko Ursulin authored
MMIO addresses and register definition for the new interrupt registers in Gen11. v2: Removed spelt out VCS and VECS bit definitions. (Daniel Vetter) v3: Adjust VCS and VECS. (Daniele Ceraolo Spurio) v4: Bikeshedding (Paulo). Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
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Anusha Srivatsa authored
Add the PCI ID for the ICL PCH - ICP. v2: rebased. v3: rebased. v4: fix ICP name. v5: fix the ID mask (Fei Li). v6 (from Paulo): bikesheds. Cc: Li, Fei <fei.li@intel.com> Reviewed-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
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Anusha Srivatsa authored
In ICP, there are three TC ports and 3 DDI ports. v2: - Correct Pin mapping. v3: - Update pin mapping into per platform implementation rather than previous approach of port wise mapping. v4: - Update GMBUS_NUM_PINS (Paulo) v5: - rebase. v6: - Update function name, GMBUS_PIN_NUM (Paulo) v7 (from Paulo): - Make it apply. v8 (from Paulo): - Maintain consistent if ladder ordering. Suggested by: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Anusha Srivatsa authored
ICP has two backlight controllers - similar to previous platforms like BXT -, but we only use one controller for now, so we can just reuse the CNP code. v2: Remove the usage of ICP_SECOND_PPS_BACKLIGHT register.(Jani) Reuse CNP code since it is very similar.(Ville) v3 (from Paulo): Rebase. v4 (from Paulo): adjust commit message (James) and comment (Rodrigo). Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Acked-by:
James Ausmus <james.ausmus@intel.com> Reviewed-by:
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Anusha Srivatsa authored
ICP, like BXT, has has two panel power sequencers. v2: Simplify the code. Remove unwanted register definitions. Make code as close to BXT style as possible. (Ville) Also, remove the use of ICP_SECOND_PPS_BACKLIGHT for now. Moving forward, if we are sure we need to set this register, we can access it. v3: Use INTEL_GEN(dev_priv), make code more readeable. (Ville) v4 (from Paulo): - Coding style fixes. - Add a missing HAS_PCH_CNP -> gen10+ check. - Rebase. v5: Use per platform checks rather than INTEL_GEN(). v4 of this patch breaks on CoffeeLake, since CFL uses CNP and per platform check makes sense in that case. v6 (from Paulo): - v5 was a patch on top of v4, not a new version. Now v6 is correctly a new version of the original patch. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by: -
Anusha Srivatsa authored
Add register definitions for setting the rawclock. Set the numerator,denominator and divider values. v2: Simplify the commit message. Simplify the math. Add register bits for numerator. (Paulo) v3 (from Paulo): coding style bikesheds. Reviewed-by:
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Anusha Srivatsa authored
Add the enum additions to ICP PCH. v2 (from Paulo): don't set any platforms to it yet since ICP support is incomplete. v3 (from Rodrigo): Fix ICP name. Reviewed-by:
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Rodrigo Vivi authored
Icelake is an Intel
® Processor containing an Intel® Graphics Controller. This is just an initial Icelake definition. PCI IDs, Icelake support and new features coming in following patches. v2: Add .ddb_size and .has_guc (Michal Wajdeczko). v3: Add the ICL_FEATURES macro (Kelvin Gardiner). v4 (from Paulo): Add missing __initconst (Paulo) and say "graphics controller" instead of something that looks like an official marketing name but isn't (Chris). Reviewed-by: -
Rodrigo Vivi authored
Some Cannonlake SKUs will come with a full split between port A and port E. This will be called port F although it is not a 6th port, but only a split. Note this patch alone is not sufficient for port F enabling, it's just the first step. v2: Fix size of dvo_ports found by Ander. v3: Adding missing cases from intel_bios.c for Port_F v4: Adding other missing cases and fix the commit message. v5: Rebase on top of display headers rework. v6 (from Paulo): improve commit message, bikeshed bit definitions. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Acked-by:
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Mika Kahola authored
We may have fused or unused pipes in our system. Let's check that the pipe in question is within limits of accessible pipes. In case, that we are not able to access the pipe, we return early with a warning. v2: Rephrasing of the commit message (Jani) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103206Reported-by:
Thomas Gleixner <tglx@linutronix.de> Tested-by:
Jaswinder Singh Rajput <jaswinder@perfectintelligent.com> Suggested-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Ville Syrjälä authored
SKL+ "sprites" no longer have 16KB max stride limit that earlier platforms had. Bump up the limit to 32KB. Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Stone <daniels@collabora.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171222192231.17981-7-ville.syrjala@linux.intel.comReviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Ville Syrjälä authored
Allow sprites to scan out compressed framebuffers. Since different platforms have a different set of planes that support CCS let's add a small helper to determine whether a specific plane supports CCS or not. Currently that information is spread around in many places, and not all the pieces of code even agree with each other. In addition to allowing sprites to scan out compressed fbs, the other fix here is that we stop rejecting them on pipe C on CNL. Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Stone <daniels@collabora.com> Signed-off-by:
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Ville Syrjälä authored
Split the g4x and snb cases into separate functions to match how we deal with all other platforms. Also sort the switch cases to match the format lists we've declared earlier, to ease comparisons. Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Stone <daniels@collabora.com> Signed-off-by:
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Ville Syrjälä authored
Y/Yf were dropped out from the SKL+ sprite modifier list on account of some watermark issues Daniel Stone was having. My subsequent testing seemed to indicate that things work better now, so add the modifiers back in. v2: Update the commit message with a better explanation Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Stone <daniels@collabora.com> Signed-off-by:
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Ville Syrjälä authored
The unreachable() is very much unreachable and the compiler knows that, so there's no point in having it. Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Stone <daniels@collabora.com> Signed-off-by:
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Abdiel Janulgue authored
4K modes testing by using dummy EDID data has never been working properly on boxes with DP++ (dual-mode) adaptors. The reason for this is that those modes got pruned during hdmi mode validation. intel_hdmi_mode_valid returns CLOCK_HIGH because the pixel clock reported by the 4k mode is higher than dual port TMDS clock limit. However 4k injection does work properly on machines that don't have DP++ adapters because the mode is never validated against the DP++ TMDS clock limit. v2: Don't detect the DP++ limits when we're testing using overridden EDIDs. Make sure to check for the override condition after respecting the value of drm_dp_dual_mode_detect (Jani Nikula). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101649 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by:
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Jani Nikula authored
drm_edid_to_eld() sets ELD connector type since commit 1d1c3665 ("drm/edid: set ELD connector type in drm_edid_to_eld()"). Remove the redundant update. (Commit c945b8c1 ("drm/edid: build ELD in drm_add_edid_modes()") and commit d471ed04 ("drm/drivers: drop redundant drm_edid_to_eld() calls") are also related.) v2: Rebase, update commit message with commit references. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Acked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Jani Nikula authored
No more sing-a-ling. Reported-by:
Adam Jackson <ajax@redhat.com> You're-my-ding-a-ling-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
David Weinehall <david.weinehall@linux.intel.com> Signed-off-by:
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- 18 Jan, 2018 8 commits
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Jani Nikula authored
Update VBT defs to reflect revision 216. While at it, default the expected child device struct size to sizeof the size rather than a hardcoded value. v2: Fix bit order (David) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Lucas De Marchi authored
Display WA #1178 is meant to fix Aux channel voltage swing too low with some type C dongles. Although it is for type C, HW engineers reported that it can be applied to all external ports even if they are not going to type C. For CNL we apply the workaround every time Aux B, C and D are powering up since they will lose the configuration when powered down. v2: Use common tag for WA Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Arthur J Runyan <arthur.j.runyan@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Michel Thierry authored
Instead of using local string names that we will have to keep maintaining, use the engine->name directly. v2: Better invalid engine_id handling, capture_bo will not be able know the engine_id and end up with -1 (Michal). Suggested-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by:
Michel Thierry <michel.thierry@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180118175228.2830-1-chris@chris-wilson.co.uk
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Michal Wajdeczko authored
Today we have format mismatch between read/write operations of i915_guc_log_control entry. For read we return (0, 1..4) that represents disable/verbosity levels, but for write we force user to follow internal structure format (0,1,9,11,13). Let's hide internals from the user and accept same values as we support for read and related guc_log_level modparam. Signed-off-by:
Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by:
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Michal Wajdeczko authored
We used value -1 to indicate "disabled" and values 0..3 to indicate "enabled", but most of our other modparams are using -1 for "auto" mode and 0 for "disable". For consistency let's change our log level values to: -1: auto (depends on platform and Kconfig.debug settings) 0: disabled 1: enabled (severity level 0 = min) 2: enabled (severity level 1) 3: enabled (severity level 2) 4: enabled (severity level 3 = max) v2: fix commit message (Sagar) display sanitized modparam value (Sagar) unify sanitize messages (Sagar/Michal) Signed-off-by: -
Chris Wilson authored
Watching a light workload on Baytrail (running glxgears and a 1080p decode), instead of the system remaining at low frequency, the glxgears would regularly trigger waitboosting after which it would have to spend a few seconds throttling back down. In this case, the waitboosting is counter productive as the minimal wait for glxgears doesn't prevent it from functioning correctly and delivering frames on time. In this case, glxgears happens to almost always be waiting on the current request, which we already expect to complete quickly (see i915_spin_request) and so avoiding the waitboost on the active request and spinning instead provides the best latency without overcommitting to upclocking. However, if the system falls behind we still force the waitboost. Similarly, we will also trigger upclocking if we detect the system is not delivering frames on time - again using a mechanism that tries to detect a miss and not preemptively upclock. v2: Also skip boosting for after missed vblank if the desired request is already active. Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180118131609.16574-1-chris@chris-wilson.co.uk
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Imre Deak authored
The CDCLK bypass frequency can vary on upcoming platforms, so prepare for that now by tracking its value in the CDCLK state. Currently on BDW+ the bypass frequency is always the reference clock and I didn't bother with earlier platforms since it's not all that clear what's the bypass clock on those. I also didn't bother adding support for changing this frequency, since atm I don't see any need for it. Suggested-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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Chris Wilson authored
Since commit 4e773c3a ("drm/i915: Wire up shrinkctl->nr_scanned"), we track the number of objects we scan and do not wish to exceed that as it will overly penalise our own slabs under mempressure. Given that we now know the target number of objects to scan, use that as our guide for deciding to shrink as opposed to the number of objects we manage to shrink (which doesn't correspond to the numbers we report to shrinkctl). Fixes: 4e773c3a ("drm/i915: Wire up shrinkctl->nr_scanned") Signed-off-by:
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- 17 Jan, 2018 3 commits
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Arnd Bergmann authored
struct timeval is deprecated because it cannot represent times past 2038. In this driver, the only use of this structure is to capture debug information. This is easily changed to ktime_t, which we then format as needed when printing it later. Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Link: https://patchwork.freedesktop.org/patch/msgid/20180117154916.219273-1-arnd@arndb.deSigned-off-by:
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Chris Wilson authored
When testing that the timeout fired, we need to be sure we have waited just long enough for the timeout to have occurred and for the softirq (on another cpu) to have completed. Sleeping for an arbitrary amount is prone to error, so wait for the timeout instead and complain if it was too late. v2: Use wait_event_timeout to provide an upper bound v3: Fix inverted check for wait_event_timeout timing out v4: Restore the check that the fences aren't signalled too early, by inspecting them before the expected timeout. References: https://bugs.freedesktop.org/show_bug.cgi?id=104670Signed-off-by:
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Maarten Lankhorst authored
It's perfectly legal to create a fb with stride < 512, and one of the kms_plane_scaling subtests creates a very small fb. Downgrade the WARN_ON to a simple check check, and because this function is potentially called on every atomic update/pageflip, downgrade the other WARN_ON to a WARN_ON_ONCE, and do the right thing here. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180116155331.75175-1-maarten.lankhorst@linux.intel.comReviewed-by:
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- 16 Jan, 2018 3 commits
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Maarten Lankhorst authored
intel_power_domains_init_hw() calls set_init_power, but when using runtime power management this call is skipped. This prevents hw readout from taking place. Signed-off-by:
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Chris Wilson authored
Tvrtko noticed that the comments describing the interaction of RCU and the deferred worker for freeing drm_i915_gem_object were a little confusing, so attempt to bring some sense to them. Signed-off-by:
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Chris Wilson authored
Check that we can successfully wait upon a dma_fence using the i915_sw_fence, including the optional timeout mechanism. v2: Account for the rounding up of the timeout to the next second. Unfortunately, the minimum delay is then 1 second. Signed-off-by:
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- 15 Jan, 2018 4 commits
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Chris Wilson authored
As freeing the objects require serialisation on struct_mutex, we should prefer to use our singlethreaded driver wq that is dedicated to work requiring struct_mutex (hence serialised).The benefit should be less clutter on the system wq, allowing it to make progress even when the driver/struct_mutex is heavily contended. Signed-off-by:
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Chris Wilson authored
In order to prevent a race condition where we may end up overaccounting the active state and leaving the busy-stats believing the GPU is 100% busy, lock out the tasklet while we reconstruct the busy state. There is no direct spinlock guard for the execlists->port[], so we need to utilise tasklet_disable() as a synchronous barrier to prevent it, the only writer to execlists->port[], from running at the same time as the enable. Fixes: 4900727d ("drm/i915/pmu: Reconstruct active state on starting busy-stats") Signed-off-by:
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Chris Wilson authored
As the timeout mechanism has grown more and more complicated, using multiple deferred tasks and more than doubling the size of our struct, split the two implementations to streamline the simpler no-timeout callback variant. Signed-off-by:
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Chris Wilson authored
Without an accompanying timer (for internal fences), we can free the fence callback immediately as we do not need to employ the RCU barrier to serialise with the timer. By avoiding the RCU delay, we can avoid the extra mempressure under heavy inter-engine request utilisation. Signed-off-by:
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- 12 Jan, 2018 3 commits
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Dhinakaran Pandiyan authored
DPCD read for the eDP is complete by the time intel_psr_init() is called, which means we can avoid initializing PSR structures and state if there is no sink support. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by:
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Dhinakaran Pandiyan authored
The global variable dev_priv->psr.sink_support is set if an eDP sink supports PSR. Use this instead of redoing the check with is_edp_psr(). Combine source and sink support checks into a macro that can be used to return early from psr_{invalidate, single_frame_update, flush}. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: -
Dhinakaran Pandiyan authored
This flag has become redundant since commit 4d90f2d5 ("drm/i915: Start tracking PSR state in crtc state") It is set at the same place as psr.enabled, which is also exposed via debugfs. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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