- 08 Mar, 2019 3 commits
-
-
Chris Wilson authored
If we drop the engine lock, we may run execlists_dequeue which may free the priolist. Therefore if we ever drop the execution lock on the engine, we have to discard our cache and refetch the priolist to ensure we do not use a stale pointer. [ 506.418935] [IGT] gem_exec_whisper: starting subtest contexts-priority [ 593.240825] general protection fault: 0000 [#1] SMP [ 593.240863] CPU: 1 PID: 494 Comm: gem_exec_whispe Tainted: G U 5.0.0-rc6+ #100 [ 593.240879] Hardware name: /NUC6CAYB, BIOS AYAPLCEL.86A.0029.2016.1124.1625 11/24/2016 [ 593.240965] RIP: 0010:__i915_schedule+0x1fe/0x320 [i915] [ 593.240981] Code: 48 8b 0c 24 48 89 c3 49 8b 45 28 49 8b 75 20 4c 89 3c 24 48 89 46 08 48 89 30 48 8b 43 08 48 89 4b 08 49 89 5d 20 49 89 45 28 <48> 89 08 45 39 a7 b8 03 00 00 7d 44 45 89 a7 b8 03 00 00 49 8b 85 [ 593.240999] RSP: 0018:ffffc90000057a60 EFLAGS: 00010046 [ 593.241013] RAX: 6b6b6b6b6b6b6b6b RBX: ffff8882582d7870 RCX: ffff88826baba6f0 [ 593.241026] RDX: 0000000000000000 RSI: ffff8882582d6e70 RDI: ffff888273482194 [ 593.241049] RBP: ffffc90000057a68 R08: ffff8882582d7680 R09: ffff8882582d7840 [ 593.241068] R10: 0000000000000000 R11: ffffea00095ebe08 R12: 0000000000000728 [ 593.241105] R13: ffff88826baba6d0 R14: ffffc90000057a40 R15: ffff888273482158 [ 593.241120] FS: 00007f4613fb3900(0000) GS:ffff888277a80000(0000) knlGS:0000000000000000 [ 593.241133] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 593.241146] CR2: 00007f57d3c66a84 CR3: 000000026e2b6000 CR4: 00000000001406e0 [ 593.241158] Call Trace: [ 593.241233] i915_schedule+0x1f/0x30 [i915] [ 593.241326] i915_request_add+0x1a9/0x290 [i915] [ 593.241393] i915_gem_do_execbuffer+0x45f/0x1150 [i915] [ 593.241411] ? init_object+0x49/0x80 [ 593.241425] ? ___slab_alloc.constprop.91+0x4b8/0x4e0 [ 593.241491] ? i915_gem_execbuffer2_ioctl+0x99/0x380 [i915] [ 593.241563] ? i915_gem_execbuffer_ioctl+0x270/0x270 [i915] [ 593.241629] i915_gem_execbuffer2_ioctl+0x1bb/0x380 [i915] [ 593.241705] ? i915_gem_execbuffer_ioctl+0x270/0x270 [i915] [ 593.241724] drm_ioctl_kernel+0x81/0xd0 [ 593.241738] drm_ioctl+0x1a7/0x310 [ 593.241803] ? i915_gem_execbuffer_ioctl+0x270/0x270 [i915] [ 593.241819] ? __update_load_avg_se+0x1c9/0x240 [ 593.241834] ? pick_next_entity+0x7e/0x120 [ 593.241851] do_vfs_ioctl+0x88/0x5d0 [ 593.241880] ksys_ioctl+0x35/0x70 [ 593.241894] __x64_sys_ioctl+0x11/0x20 [ 593.241907] do_syscall_64+0x44/0xf0 [ 593.241924] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 593.241940] RIP: 0033:0x7f4615ffe757 [ 593.241952] Code: 00 00 90 48 8b 05 39 a7 0c 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 09 a7 0c 00 f7 d8 64 89 01 48 [ 593.241970] RSP: 002b:00007ffc1030ddf8 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 593.241984] RAX: ffffffffffffffda RBX: 00007ffc10324420 RCX: 00007f4615ffe757 [ 593.241997] RDX: 00007ffc1030e220 RSI: 0000000040406469 RDI: 0000000000000003 [ 593.242010] RBP: 00007ffc1030e220 R08: 00007f46160c9208 R09: 00007f46160c9240 [ 593.242022] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000040406469 [ 593.242038] R13: 0000000000000003 R14: 0000000000000000 R15: 0000000000000000 [ 593.242058] Modules linked in: i915 intel_gtt drm_kms_helper prime_numbers v2: Track the local engine cache and explicitly clear it when switching engine locks. Fixes: a02eb975 ("drm/i915/execlists: Cache the priolist when rescheduling") Testcase: igt/gem_exec_whisper/contexts-priority # rare! Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190211204647.26723-1-chris@chris-wilson.co.uk (cherry picked from commit ed7dc677) Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com>
-
Chris Wilson authored
If we allocate while iterating the rbtree of active nodes, we may hit the shrinker and so retire the i915_active, reaping the rbtree. Modifying the rbtree as we iterate is not good behaviour, so acquire the i915_active first to keep the tree intact whenever we allocate. Fixes: a42375af ("drm/i915: Release the active tracker tree upon idling") Signed-off-by:
-
Ramalingam C authored
The downgrade of the fullmodeset into fastset intel_encoder->update_pipe, in possible scenario, skips the En/Dis-able DDI. Hence breaks the HDCP state change handling. We also don't have any hdcp tests in CI, because the shard runs don't have hdcp capable outputs :-/ So this change fixs it by handling the HDCP state change request at intel_encoder->update_pipe too along with enable and disable of the DDI. Fixes: d19f958d ("drm/i915: Enable fastset for non-boot modesets.") v2: Added commit id that broke the HDCP [Daniel] Signed-off-by:
Ramalingam C <ramalingam.c@intel.com> cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> cc: Hans de Goede <hdegoede@redhat.com> cc: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1549295080-18353-1-git-send-email-ramalingam.c@intel.com (cherry picked from commit 634852d1) Signed-off-by:
-
- 14 Feb, 2019 1 commit
-
-
git://anongit.freedesktop.org/drm/drm-miscDaniel Vetter authored
drm-misc-next for 5.1: UAPI Changes: - New fourcc for P010 and P016 formats Cross-subsystem Changes: Core Changes: - Removal of drm_calc_{h,v}scale_relaxed - A few fixes for DP-MST Driver Changes: - More drmP.h cleanups - A bunch of vkms fixes - Conversion of the Cadence DSI bridge and Allwinner DSI driver to the generic phy MIPI-DPHY API - New panel: Innolux EE101IA-01D Signed-off-by:
-
- 11 Feb, 2019 8 commits
-
-
Sam Ravnborg authored
With drmP.h removed from drm_modeset_helper.h the build of komeda filed as reported by linux-next Add missing include files to fix build. For the files touched group include files and sort them. The fix was tested on a tree with drm-misc-next merged. And the patch was also tested to work without drm-misc-next merged. Build tested on arm + x86. Signed-off-by:
Sam Ravnborg <sam@ravnborg.org> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> [linux-next] Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: James Wang <james.qian.wang@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Brian Starkey <brian.starkey@arm.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190208221324.27002-1-sam@ravnborg.org
-
Maxime Ripard authored
We need to backmerge drm-next to fix the komeda build failure. Signed-off-by: -
Shayenne Moura authored
Remove KMS cleanup task from documentation solved by patchset https://patchwork.freedesktop.org/series/54310/Signed-off-by:
Shayenne Moura <shayenneluzmoura@gmail.com> Signed-off-by:
-
Gerd Hoffmann authored
Bisected guest kernel changes crashing qemu. Landed at "6c1cd97b drm/virtio: fix resource id handling". Looked again, and noticed we where not only leaking *some* ids, but *all* ids. The old code never ever called virtio_gpu_resource_id_put(). So, commit 6c1cd97b effectively makes the linux kernel starting re-using IDs after releasing them, and apparently virglrenderer can't deal with that. Oops. This patch puts a temporary stopgap into place for the 5.0 release. Signed-off-by:
Gerd Hoffmann <kraxel@redhat.com> Reviewed-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
-
git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
Updates for 5.1: - GDS fixes - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES interface - GPUVM fixes - PCIE DPM switching fixes for vega20 - Vega10 uclk DPM regression fix - DC Freesync fixes - DC ABM fixes - Various DC cleanups Signed-off-by:
-
git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
UAPI Changes: - Expose RPCS (SSEU) configuration to userspace for Ice Lake in order to allow userspace to reconfigure the subslice config per context basis. (Tvrtko, Lionel) Driver Changes: - Execbuf and preemption improvements including selftests (Chris) - Rename HAS_GMCH_DISPLAY/HAS_GMCH (Rodrigo) - Debugfs error handling fix for robustness (Greg) - Improve reg_rw traces (Ville) - Push clear_intel_crtc_state onto the heap (Chris) - Watermark fixes for Ice Lake (Ville) - Fix enable count array size and bounds checking (Tvrtko) - MST Fixes (Lyude) - Prevent race and handle error on I915_GEM_MMAP (Joonas) - Initial rework for an full atomic gamma mode (Ville) Signed-off-by:
-
git://anongit.freedesktop.org/tegra/linuxDave Airlie authored
drm/tegra: Changes for v5.1-rc1 This set of changes starts of with some refactoring of the CEC support to make it reusable on Tegra210 and later. Following are a couple of fixes for HDMI audio support (via HDA). The bulk here is a set of preparatory patches working towards enabling Tegra186 support for host1x and VIC. Additional patches will be needed to fully enable this, but they're not quite ready yet. To round things off, this also adds support for configuring the SOR crossbar using device tree, and fixes a couple of job-related issues in the host1x code. Signed-off-by:
-
git://linuxtv.org/pinchartl/mediaDave Airlie authored
Renesas display drivers changes for v5.1 (2nd part): - R8A7744 LVDS support - DPAD0 output support on D3/E3 Signed-off-by:
-
- 10 Feb, 2019 1 commit
-
-
Shayenne Moura authored
Add a warn to verify the hrtimer_forward_now return and changes ret_overrun from int to u64 to match the return value provided by hrtimer_forward_now. Signed-off-by:
Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190206200813.d5w7gjpepoeeadiy@smtp.gmail.com
-
- 08 Feb, 2019 11 commits
-
-
Manasi Navare authored
This patch adds appropriate kernel documentation for DRM DP helpers used for enabling Display Stream compression functionality in drm_dp_helper.h and drm_dp_helper.c as well as for the DSC spec related structure definitions and helpers in drm_dsc.c and drm_dsc.h Also add links between the functions and structures in the documentation. v3: * Fix the checkpatch warnings (Sean Paul) v2: * Add inline comments for longer structs (Daniel Vetter) * Split the summary and description (Daniel Vetter) Suggested-by:
Daniel Vetter <daniel.vetter@intel.com> Suggested-by:
Sean Paul <sean@poorly.run> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Sean Paul <sean@poorly.run> Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> Acked-by:
-
Randy Li authored
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per channel video format. P012 is a planar 4:2:0 YUV 12 bits per channel P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per channel video format. V3: Added P012 and fixed cpp for P010. V4: format definition refined per review. V5: Format comment block for each new pixel format. V6: reversed Cb/Cr order in comments. v7: reversed Cb/Cr order in comments of header files, remove the wrong part of commit message. V8: reversed V7 changes except commit message and rebased. v9: used the new properties to describe those format and rebased. Cc: Daniel Stone <daniel@fooishbar.org> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Randy Li <ayaka@soulik.info> Signed-off-by:
Clint Taylor <clinton.a.taylor@intel.com> Reviewed-by:
Ayan Kumar Halder <ayan.halder@arm.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
-
Maxime Ripard authored
Since the DPHY rework, one error path doesn't set the return error code before jumping to its error label, which in turns make gcc (rightfully) complain about the variable holding the error code being uninitialized. Fix this. Fixes: bb3b6fcb ("sun6i: dsi: Convert to generic phy handling") Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by:
-
Dave Airlie authored
Merge tag 'exynos-drm-next-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next - Add rotator support for s5pv210 . With this patch series, s5pv210 SoC can use rotator module but only NV12 and XRGB8888 formats are supported. - Modify e-mail address . It changes email address of scaler module author. Signed-off-by:
-
Laurent Pinchart authored
On the D3 and E3 SoCs the LVDS PLL clock output provides the dot clock to the DU channels, even when the LVDS outputs are not in use. Enable and disable the LVDS clock output when enabling or disabling a CRTC connected to the DPAD0 output. Signed-off-by:Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
-
Laurent Pinchart authored
On the D3 and E3 platforms, the LVDS internal PLL supplies the pixel clock to the DU. This works automatically for LVDS outputs as the LVDS encoder is enabled through the bridge API, enabling the internal PLL and clock output. However, when using the DU DPAD output with the LVDS outputs turned off, the LVDS PLL needs to be controlled manually. Add an API to do so, to be called by the DU driver. The drivers/gpu/drm/rcar-du/ directory has to be treated as obj-y unconditionally, as the LVDS driver could be built-in while the DU driver is compiled as a module. Signed-off-by: -
Laurent Pinchart authored
On the D3 and E3 SoCs the LVDS encoder has an extended internal PLL and supplies a clock to the DU. That clock is used not only for the LVDS outputs but also for the DPAD output. The LVDS encoder thus needs to be available to the DU even when its output is disabled. Don't fail probe in that case on D3 and E3. Signed-off-by: -
Laurent Pinchart authored
Before the driver fully moved to drm_bridge and drm_panel, it was necessary to parse DT and locate encoder and connector nodes. The connector node is now unused and can be removed as a parameter to rcar_du_encoder_init(). As a consequence rcar_du_encoders_init_one() can be greatly simplified, removing most of the DT parsing. Signed-off-by: -
Biju Das authored
The LVDS encoders on RZ/G1N SoC is similar to RZ/G1M. Add support for RZ/G1N (R8A7744) SoC to the LVDS encoder driver. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au>
-
Biju Das authored
Document the RZ/G1N (R8A7744) LVDS bindings. Signed-off-by:
Rob Herring <robh@kernel.org>
-
Julia Lawall authored
Add an of_node_put when the result of of_graph_get_remote_port_parent is not available. Add a second of_node_put if no encoder is selected (encoder remains NULL). The semantic match that finds the first problem is as follows (http://coccinelle.lip6.fr): // <smpl> @r exists@ local idexpression e; expression x; @@ e = of_graph_get_remote_port_parent(...); ... when != x = e when != true e == NULL when != of_node_put(e) when != of_fwnode_handle(e) ( return e; | *return ...; ) // </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Reviewed-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by:
-
- 07 Feb, 2019 16 commits
-
-
Harry Wentland authored
dal_gpio_open and dal_gpio_unlock_pin dereference hpd_gpio. Check for NULL before calling those functions. Fixes: ac627caf ("drm/amd/display: add gpio lock/unlock") Reported-by:
Przemek Socha <soprwa@gmail.com> CC: Chiawen Huang <chiawen.huang@amd.com> CC: Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Tested-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
-
Sam Ravnborg authored
With the removal of drmP.h from drm_modeset_helper.h the drmP.h are no longer included by any include files in include/drm. The drmP.h file is thus only included explicit either in .c files or in local .h files. This makes the process of deleting the drmP.h includes easier as we have a more local dependency chain. v2: - moved updates of .c files in drm/ to a dedicated patch. This allows the updates to the *.c files to be committed without the removal part. So this patch can wait if it causes build failures due to pending changes Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Sean Paul <sean@poorly.run> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by:
-
Sam Ravnborg authored
The use of drmP.h is discouraged and removal of it from drm_modeset_helper.h caused drm/ to fail to build. This patch introduce the necessary fixes to prepare for the drmP.h removal from drm_modeset_helper.h. Build tested on x86, arm, alpha, ia64 allmodconfig/allyesconfig. Signed-off-by:
-
Sam Ravnborg authored
The use of drmP.h is discouraged and removal of it from drm_modeset_helper.h caused rcar-du to fail to build. This patch introduce the necessary fixes to prepare for the drmP.h removal from drm_modeset_helper.h. Build tested on arm allmodconfig/allyesconfig. v2: - new patch. Changes like drm_probe_helper and other required several updates Signed-off-by:
-
Sam Ravnborg authored
The use of drmP.h is discouraged and removal of it from drm_modeset_helper.h caused i915 to fail to build. This patch introduce the necessary fixes to prepare for the drmP.h removal from drm_modeset_helper.h. In the files touched the lists of include files was grouped and sorted. Build tested on x86 and arm allmodconfig / allyesconfig. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
-
Sam Ravnborg authored
The use of drmP.h is discouraged and removal of it from drm_modeset_helper.h caused vboxvideo to fail to build. This patch introduce the necessary fixes to prepare for the drmP.h removal from drm_modeset_helper.h. In the files touched sort the include files Build tested on x86 and arm allmodconfig / allyesconfig. Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
-
Rodrigo Vivi authored
Signed-off-by: -
Ville Syrjälä authored
The LUTs are single buffered so we should program them after the double buffered pipe updates have been latched by the hardware. We'll also fix up the IPS vs. split gamma w/a to do the IPS disable like everyone else. Note that this is currently dead code as we don't use the split gamma mode on HSW, but that will be fixed up shortly. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190205160848.24662-7-ville.syrjala@linux.intel.comReviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
-
Ville Syrjälä authored
Split the color management hooks along the single vs. double buffered registers line. Of the currently programmed registers GAMMA_MODE and the ilk+ pipe CSC are double buffered, the LUTS and CHV CGM block are single buffered. The double buffered register will be programmed during the normal pipe update with evasion, and also during pipe enable so that the settings will already be correct when the pipe starts up before the planes are enabled. The single buffered registers are currently programmed before the vblank evade. Which is totally wrong, but we'll correct that later. v2: Add some docs to explain the two vfuncs (Matt,Uma) Rebase Signed-off-by: -
Ville Syrjälä authored
For bdw+ let's move the GAMMA_MODE write for the legacy LUT mode into the .load_luts() funciton directly, rather than relying on haswell_load_luts(). We'll be getting rid of haswell_load_luts() entirely soon, and it's anyway cleaner to have the GAMMA_MODE write in a single place. Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190205160848.24662-5-ville.syrjala@linux.intel.comReviewed-by:
-
Ville Syrjälä authored
Pass the crtc state etc. as const to the color management commit functions. And while at it polish some of the local variables. v2: Rebase Signed-off-by:
-
Ville Syrjälä authored
We shouldn't be computing gamma mode during the commit phase. Move it to the check phase. v2: Reword comments a bit (Matt) Rebase Signed-off-by: -
Ville Syrjälä authored
On g4x+ the pipe gamma enable bit for the primary plane affects the pipe bottom color as well. The same for the pipe csc enable bit on ilk+. Thus we must configure those bits correctly even when the primary plane is disabled. To make the feasible let's split those settings from the plane_ctl() function into a seprate funciton that we can call from the ->disable_plane() hook as well. For consistency we'll do that on all the plane types. While that has no real benefits at this time, it'll become useful when we start to control the pipe gamma/csc enable bits dynamically when we overhaul the color management code. On pre-g4x there doesn't appear to be any way to gamma correct the pipe bottom color, but sticking to the same pattern doesn't hurt. And it'll still help us to do crtc state readout correctly for the pipe gamma enable bit for the color management overhaul. An alternative apporach would be to still precompute these bits into plane_state->ctl, but that would require that we run through the plane check even when the plane isn't logically enabled on any crtc. Currently that condition causes us to short circuit the entire thing and not call ->check_plane(). There would also be some chicken and egg problems with ->check_plane() vs. crtc color state check that would requite splitting certain things into multiple steps. So all in all this seems like the easier route. Signed-off-by:
-
Christian König authored
The exclusive fence is of course perfectly optional here. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
-
Harish Kasiviswanathan authored
v2: Fix SMU message format Send override message after SMU enable features Signed-off-by:Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
Eric Huang <JinhuiEric.Huang@amd.com> Signed-off-by:
-
Harish Kasiviswanathan authored
The new Vega series GPU cards have in-built bridges. To get the pcie speed and width supported by the platform walk the hierarchy and get the slowest link. Signed-off-by:
-
