- 15 Oct, 2019 20 commits
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Hersen Wu authored
there are two paths for renoir dc access smu. one dc access smu directly using bios smc interface: set disply, dprefclk, etc. another goes through pplib for get dpm clock table and set watermmark. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
Enable runtime VCN DPM on/off on Arcturus. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Kenneth Feng authored
Bug fix for pcie paramerers override on swsmu. Below is a scenario to have this problem. pptable definition on pcie dpm: 0 -> pcie gen speed:1, pcie lanes: *16 1 -> pcie gen speed:4, pcie lanes: *16 Then if we have a system only have the capbility: pcie gen speed: 3, pcie lanes: *8, we will override dpm 1 to pcie gen speed 3, pcie lanes *8. But the code skips the dpm 0 configuration. So the real pcie dpm parameters are: 0 -> pcie gen speed:1, pcie lanes: *16 1 -> pcie gen speed:3, pcie lanes: *8 Then the wrong pcie lanes will be toggled. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Emily Deng authored
When index is 1, need to set compute ring timeout for sriov and passthrough. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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Christian König authored
When we allocate new page tables under memory pressure we should not evict old ones. Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
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Christian König authored
We need to drop normal and userptr BOs separately. Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Dennis Li authored
v1: Add codes to query the EDC count of VML2 & ATCL2 v2: Rename VML2/ATCL2 registers and drop their mask define v3: Add back the ECC mask for VML2 registers Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
Hawking Zhang <hawking.zhang@amd.com> Acked-by:
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Dennis Li authored
Add VML2 and ATCL2 ECC registers to support VEGA20 RAS Signed-off-by:
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Dennis Li authored
For the potential request in the future, change to query the actual EDC counter. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Le Ma authored
BACO reset is needed for RAS recovery. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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Le Ma authored
1 indicates RAS recovery flag in SMU FW. Signed-off-by:
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Le Ma authored
Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting for ECC supported SKU. Signed-off-by:
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Le Ma authored
Workaround to make RAS recovery work in BACO reset. Signed-off-by:
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Hans de Goede authored
Bail from the pci_driver probe function instead of from the drm_driver load function. This avoid /dev/dri/card0 temporarily getting registered and then unregistered again, sending unwanted add / remove udev events to userspace. Specifically this avoids triggering the (userspace) bug fixed by this plymouth merge-request: https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59 Note that despite that being a userspace bug, not sending unnecessary udev events is a good idea in general. BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Alex Deucher authored
Use the dcn21 functions in dcn21_resource.c and make the dcn20 functions static since they are only used in dcn20_resource now. Cc: bhawanpreet.lakha@amd.com Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Xiaojie Yuan authored
SMU firmware has fix the bug, so remove this workaround. Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by:
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Xiaojie Yuan authored
IP Discovery data is TMR fenced by the latest PSP BL, so we need to reserve this region. Tested on navi10/12/14 with VBIOS integrated with latest PSP BL. v2: use DISCOVERY_TMR_SIZE macro as bo size use amdgpu_bo_create_kernel_at() to allocate bo Signed-off-by: -
Kevin Wang authored
add navi14 umd pstate peak clock support. NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK 1670 MHz NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK 1448 MHz NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK 1181 MHz NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK 1717 MHz NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK 1448 MHz Signed-off-by:
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Evan Quan authored
Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by:
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Evan Quan authored
Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by:
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- 11 Oct, 2019 20 commits
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Alex Deucher authored
Add toggles for more power features. Helpful in debugging. Reviewed-by:
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Ville Syrjälä authored
@swap@ identifier TEMP; expression A,B; @@ - TEMP = A; - A = B; - B = TEMP; + swap(A, B); @@ type T; identifier swap.TEMP; @@ ( - T TEMP; | - T TEMP = {...}; ) ... when != TEMP Cc: Rex Zhu <rex.zhu@amd.com> Cc: Evan Quan <evan.quan@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Ville Syrjälä authored
Mostly a cocci-job, but it flat out refused to remove the declaration in drivers/gpu/drm/amd/display/dc/core/dc.c so had to do that part manually. @swap@ identifier TEMP; expression A,B; @@ - TEMP = A; - A = B; - B = TEMP; + swap(A, B); @@ type T; identifier swap.TEMP; @@ ( - T TEMP; | - T TEMP = {...}; ) ... when != TEMP Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by:Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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chen gong authored
Find that ring sdma0 test failed if turn on SDMA powergating after do mode2 reset. Perhaps the mode2 reset does not reset the SDMA PG state, SDMA is already powered up so there is no need to ask the SMU to power it up again. So I skip this function for a moment. Signed-off-by:
chen gong <curry.gong@amd.com> Reviewed-by:
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Xiaojie Yuan authored
Additional features that can be enabled in the SMU. Signed-off-by:
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Xiaojie Yuan authored
sdma will hang once sequence number to be polled reaches 0x1000_0000 Signed-off-by:
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Alex Deucher authored
Polaris and vegam use count for the value rather than level. This looks like a copy paste typo from when the code was adapted from previous asics. I'm not sure that the SMU actually uses this value, so I don't know that it actually is a bug per se. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=108609Reported-by:
Robert Strube <rstrube@gmail.com> Reviewed-by:
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Nirmoy Das authored
cleanup error handling code and make sure temporary info array with the handles are freed by amdgpu_bo_list_put() on idr_replace()'s failure. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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Tao Zhou authored
check whether a page is bad page before umc error injection, bad page should not be accessed again Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Luben Tuikov authored
Use the ALIGN() macro to set "num_dw" to a multiple of 8, i.e. lower 3 bits cleared. Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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Alex Deucher authored
We recently added it, but never documented it. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Alex Deucher authored
Fix a couple of spelling typos. Reviewed-by:
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Dmytro Laktyushkin authored
Doing this allows us to split it for diffrent asics. This design will be helpful for future Asciis. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Eric Yang authored
[Why] Previously SMU was giving us 0s for the clock table. Now they have valid clock table. We should use theirs. Also, need to send SMU watermark ranges for selecting optimal watermarks. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Signed-off-by:
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Sung Lee authored
[WHY] Without a check for virtual links, every link's DIG was getting checked for enabled or disabled. If link was virtual, since it did not have a DIG, this would cause issues. [HOW] Skip DIG Enable check if link is virtual and add virtual link to to display count. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Wayne Lin authored
[Why] HDMI 2.0 requires scrambling under specific conditions. We refer to stream property LTE_340MCSC_SCRAMBLE to determine whether en/dis scrambling. While creating stream for sink, we setup LTE_340MCSC_SCRAMBLE by referring to edid_caps. However, dm_helpers_parse_edid_caps() doesn't construct HDMI Forum block data for edid_caps. Moreover, fill_stream_properties_from_drm_display_mode() aslo unconsciously clear the LTE_340MCSC_SCRAMBLE flag. [How] Drm already provides drm_display_info to refer HDMI Forum vsdb info. Set stream LTE_340MCSC_SCRAMBLE by drm_display_info and remove memset in fill_stream_properties_from_drm_display_mode() Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
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David Galiffi authored
[WHY] During detection: function: get_active_converter_info populates link->dpcd_caps.dongle_caps only when dpcd_rev >= DPCD_REV_11 and DWN_STRM_PORTX_TYPE is DOWN_STREAM_DETAILED_HDMI or DOWN_STREAM_DETAILED_DP_PLUS_PLUS. Otherwise, it is not cleared, and stale information remains. During mode validation: function: dp_active_dongle_validate_timing reads link->dpcd_caps.dongle_caps->dongle_type to determine the maximum pixel clock to support. This information is now stale and no longer valid. [HOW] dp_active_dongle_validate_timing should be using link->dpcd_caps->dongle_type instead. Signed-off-by:
David Galiffi <david.galiffi@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Jaehyun Chung authored
[Why] Static ramp to max refresh rate does not have capability check on calculated v_total. Programming a lower v_total_min and max than the total causes continuous spurious HPDs. [How] Add a capability check after v_total calculation similar to calculate v_total helper functions. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
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Xiaodong Yan authored
[why] 1. defer delay and sw start delay has been mixed up, defer delay was programmed to AUX_SW_CONTROL:AUX_SW_START_DELAY. 2. There's no delay for defer [how] 1. Set aux sw start to 0 2. Add delay for defer scenario Signed-off-by:
Xiaodong Yan <Xiaodong.Yan@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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