- 13 Nov, 2019 8 commits
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Nicholas Kazlauskas authored
The DMUB service is the interface to the DMCUB. It's required to support Renoir features so it will be enabled and compiled automatically when the Renoir display engine is enabled via CONFIG_DRM_AMD_DC_DCN2_1. DMUB code will initially be guarded by CONFIG_DRM_AMD_DC_DMUB and later switched to CONFIG_DRM_AMD_DC_DCN2_1 with the config option dropped. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
The interface to the DMCUB won't be through DC itself. DC will instead call into the DMUB interface introduced with a future change. The CONFIG_DRM_AMD_DC_DMUB defines will still be used for now but will be dropped at the end of the series. Since this define was never configurable in the first place this code wasn't used. Signed-off-by:
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Nicholas Kazlauskas authored
DMCUB ucode requires secure loading through PSP. This is already supported in PSP as GFX_FW_TYPE_DMUB, it just needs to be mapped from AMDGPU_UCODE_ID_DMCUB to GFX_FW_TYPE_DMUB. DMUB is a shorthand name for DMCUB and can be used interchangeably. Signed-off-by:
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Nicholas Kazlauskas authored
The DMCUB is a secondary DMCU (Display MicroController Unit) that has its own separate firmware. It's required for DMCU support on Renoir. Signed-off-by:
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Colin Ian King authored
Currently pointer aconnector is being dereferenced by the call to to_dm_connector_state before it is being null checked, this could lead to a null pointer dereference. Fix this by checking that aconnector is null before dereferencing it. Addresses-Coverity: ("Dereference before null check") Reviewed-by:Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Mikita Lipski authored
- Adding encoder atomic check to find vcpi slots for a connector - Using DRM helper functions to calculate PBN - Adding connector atomic check to release vcpi slots if connector loses CRTC - Calculate PBN and VCPI slots only once during atomic check and store them on crtc_state to eliminate redundant calculation - Call drm_dp_mst_atomic_check to verify validity of MST topology during state atomic check v2: squashed previous 3 separate patches, removed DSC PBN calculation, and added PBN and VCPI slots properties to amdgpu connector v3: - moved vcpi_slots and pbn properties to dm_crtc_state and dc_stream_state - updates stream's vcpi_slots and pbn on commit - separated patch from the DSC MST series v4: - set vcpi_slots and pbn properties to dm_connector_state - copy porperties from connector state on to crtc state v5: - keep the pbn and vcpi values only on connnector state - added a void pointer to the stream state instead on two ints, because dc_stream_state is OS agnostic. Pointer points to the current dm_connector_state. v6: - Remove new param from stream v7: - Fix error with using max capable bpc v8: - squash in fix from Gustavo A. R. Silva Reviewed-by:
Lyude Paul <lyude@redhat.com> Reviewed-by:
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Alex Deucher authored
flush/cancel delayed works before doing finalization to avoid concurrently requests. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Kenneth Feng authored
sysfs interface to read pcie speed&width info on navi1x. v2: fix warning (trivial) Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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- 11 Nov, 2019 8 commits
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Matt Coffin authored
[Why] On Navi10, and presumably arcterus, updating pp_table via sysfs would not re-scale the maximum possible power limit one can set. On navi10, the SMU code ignored the power percentage overdrive setting entirely, and would not allow you to exceed the default power limit at all. [How] Adding a function to the SMU interface to get the pptable version of the default power limit allows ASIC-specific code to provide the correct maximum-settable power limit for the current pptable. v3: fix spelling (Alex) Reviewed-by:
Matt Coffin <mcoffin13@gmail.com> Signed-off-by:
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Matt Coffin authored
[Why] Before this patch, navi10 overdrive settings could not be printed via pp_od_clk_voltage [How] Implement printing for the overdrive settings for the following clocks in navi10's ppt print_clk_levels implementation: * SMU_OD_SCLK * SMU_OD_MCLK * SMU_OD_VDDC_CURVE Reviewed-by:
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Matt Coffin authored
[Why] Before this patch, there was no way to set the gfxclk voltage curve in the overdrive settings for navi10 through pp_od_clk_voltage [How] Add the required implementation to navi10's ppt dpm table editing implementation, similar to the vega20 implementation and interface. Reviewed-by:
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Matt Coffin authored
[Why] Before this patch, there was no way to use pp_od_clk_voltage on navi [How] Similar to the vega20 implementation, but using the common smc_v11_0 headers, implemented the pp_od_clk_voltage API for navi10's pptable implementation Reviewed-by:
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Jesse Zhang authored
flush/cancel delayed works before doing finalization to avoid concurrently requests. Signed-off-by:
Jesse Zhang <zhexi.zhang@amd.com> Reviewed-by:
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KyleMahlkuch authored
This fixes the formatting on one comment and consolidates the pci_get_drvdata() into the radeon_suspend_kms(). Signed-off-by:
Kyle Mahlkuch <kmahlkuc@linux.vnet.ibm.com> Signed-off-by:
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Alex Deucher authored
When a custom powerplay table is provided, we need to update the OD VDDC flag to avoid AVFS being enabled when it shouldn't be. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205393Reviewed-by:
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Hawking Zhang authored
xgmi, ras, hdcp and dtm ta are actually separated ucode and need to handled case by case to upload to psp. We support the case that ta binary have one or multiple of them built-in. As a result, the driver should check each ta binariy's availablity before decide to upload them to psp. In the terminate (unload) case, the driver will check the context readiness before perform unload activity. It's fine to keep it as is. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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- 08 Nov, 2019 5 commits
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Alex Deucher authored
When a custom powerplay table is provided, we need to update the OD VDDC flag to avoid AVFS being enabled when it shouldn't be. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205393Reviewed-by:
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Kenneth Feng authored
This is to improve the performance in the compute mode for vega10. For example, the original performance for a rocm bandwidth test: 2G internal GPU copy, is about 99GB/s. With the idle power features disabled dynamically, the porformance is promoted to about 215GB/s. Signed-off-by:
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Evan Quan authored
OD is not supported on Arcturus. Thus the pp_od_clk_voltage sysfs interface is also not supported. Signed-off-by:
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changzhu authored
It will cause modprobe atombios stuck problem in raven2 if it doesn't allow direct upload save restore list from gfx driver. So it needs to allow direct upload save restore list for raven2 temporarily. Signed-off-by:
changzhu <Changfeng.Zhu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Stephen Rothwell authored
Fixes: 83a7772b ("drm/sched: Use completion to wait for sched->thread idle v2.") Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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- 07 Nov, 2019 8 commits
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Andrey Grodzovsky authored
Problem: During GPU reset we call the GPU scheduler to suspend it's thread, those two functions in amdgpu also suspend and resume the sceduler for their needs but this can collide with GPU reset in progress and accidently restart a suspended thread before time. Fix: Serialize with GPU reset. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
When the sched thread is parked we assume ring_mirror_list is not accessed from here. Signed-off-by:
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Andrey Grodzovsky authored
This reverts commit 89b3d864. We will do a proper fix in next patch. Signed-off-by:
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Andrey Grodzovsky authored
Removes thread park/unpark hack from drm_sched_entity_fini and by this fixes reactivation of scheduler thread while the thread is supposed to be stopped. v2: Per sched entity completion. Signed-off-by:
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Jonathan Kim authored
vega20 only requires all devices be set to same pstate level for low pstate and not high. Signed-off-by:
Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by:
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Kevin Wang authored
the asic callback function of get_pcie_replay_count is not implement on navi asic, it will cause null pinter error when read this interface. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Emily Deng authored
For driver reload test, it will report "can't enable MSI (MSI-X already enabled)". Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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Oak Zeng authored
Explain fields like aper_base, agp_start etc. The definition of those fields are confusing as they are from different view (CPU or GPU). Add comments for easier understand. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
Alex Deucher <Alex.Deucher@amd.com> Reviewed-by:
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- 06 Nov, 2019 11 commits
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Alex Deucher authored
Clarify some areas, clean up formatting, add section for unrecoverable error handling. v2: fix grammatical errors Reviewed-by:
Yong Zhao <yong.zhao@amd.com> Signed-off-by:
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Alex Deucher authored
Need to set the dte flag on this asic. Port the fix from amdgpu: 5cb818b8 ("drm/amd/amdgpu: fix si_enable_smc_cac() failed issue") Reviewed-by:
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Alex Deucher authored
To properly handle the option parsing ordering. Reviewed-by:
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Pan Bian authored
The reference to object fence is dropped at the end of the loop. However, it is dropped again outside the loop. The reference can be dropped immediately after calling dma_fence_wait() in the loop and thus the dropping operation outside the loop can be removed. Reviewed-by:
Pan Bian <bianpan2016@163.com> Signed-off-by:
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Raul E Rangel authored
drivers/gpu/drm/amd/powerplay/renoir_ppt.c:186:2: error: missing braces around initializer [-Werror=missing-braces] SmuMetrics_t metrics = {0}; ^ Fixes: 8b803170 ("drm/amd/powerplay: implement sysfs for getting dpm clock") Signed-off-by:Raul E Rangel <rrangel@chromium.org> Signed-off-by:
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Pan Bian authored
The object fence is not set to NULL after its reference is dropped. As a result, its reference may be dropped again if error occurs after that, which may lead to a use after free bug. To avoid the issue, fence is explicitly set to NULL after dropping its reference. Acked-by:
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Eric Huang authored
Using unified VBIOS has performance drop in sriov environment. The fix is switching to another register instead. Signed-off-by:
Eric Huang <JinhuiEric.Huang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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changzhu authored
It needs to add warning to update firmware in gfx9 in case that firmware is too old to have function to realize dummy read in cp firmware. Signed-off-by:
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changzhu authored
The GRBM register interface is now capable of bursting 1 cycle per register wr->wr, wr->rd much faster than previous muticycle per transaction done interface. This has caused a problem where status registers requiring HW to update have a 1 cycle delay, due to the register update having to go through GRBM. For cp ucode, it has realized dummy read in cp firmware.It covers the use of WAIT_REG_MEM operation 1 case only.So it needs to call gfx_v10_0_wait_reg_mem in gfx10. Besides it also needs to add warning to update firmware in case firmware is too old to have function to realize dummy read in cp firmware. For sdma ucode, it hasn't realized dummy read in sdma firmware. sdma is moved to gfxhub in gfx10. So it needs to add dummy read in driver between amdgpu_ring_emit_wreg and amdgpu_ring_emit_reg_wait for sdma_v5_0. Signed-off-by:
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Evan Quan authored
smu_enable_umd_pstate() will try to get the smu->mutex which was already hold by its parent API smu_force_performance_level() on the call path. Thus deadlock happens. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Evan Quan authored
P-state switch should be performed after all devices from the hive get initialized. Signed-off-by:
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