1. 12 Oct, 2011 3 commits
  2. 11 Oct, 2011 2 commits
  3. 07 Oct, 2011 10 commits
  4. 29 Sep, 2011 4 commits
    • Benjamin Herrenschmidt's avatar
      powerpc: Don't try OPAL takeover on old 970 blades · 7680057c
      Benjamin Herrenschmidt authored
      The firmware on old 970 blades supports some kind of takeover called
      "TNK takeover" which will crash if we try to probe for OPAL takeover,
      so don't do it.
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      7680057c
    • Carl E. Love's avatar
      powerpc/perf_event: Fix Power6 L1 cache read & write event codes] · d15f02eb
      Carl E. Love authored
      The current L1 cache read event code 0x80082 only counts for thread 0. The
      event code 0x280030 should be used to count events on thread 0 and 1. The
      patch fixes the event code for the L1 cache read.
      
      The current L1 cache write event code 0x80086 only counts for thread 0. The
      event code 0x180032 should be used to count events on thread 0 and 1. The
      patch fixes the event code for the L1 cache write.
      
      FYI, the documentation lists three event codes for the L1 cache read event
      and three event codes for the L1 cache write event.  The event description
      for the event codes is as follows:
      
      L1 cache read requests  0x80082  LSU 0 only
      L1 cache read requests  0x8008A  LSU 1 only
      L1 cache read requests  0x80030  LSU 1 or LSU 0, counter 2 only.
      
      L1 cache store requests 0x80086  LSU 0 only
      L1 cache store requests 0x8008E  LSU 1 only
      L1 cache store requests 0x80032  LSU 0 or LSU 1, counter 1 only.
      
      There can only be one request from either LSU 0 or 1 active at a time.
      Signed-off-by: default avatarCarl Love <cel@us.ibm.com>
      Acked-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      d15f02eb
    • Benjamin Herrenschmidt's avatar
      powerpc/ptrace: Fix build with gcc 4.6 · e69b742a
      Benjamin Herrenschmidt authored
      gcc (rightfully) complains that we are accessing beyond the
      end of the fpr array (we do, to access the fpscr).
      
      The only sane thing to do (whether anything in that code can be
      called remotely sane is debatable) is to special case fpscr and
      handle it as a separate statement.
      
      I initially tried to do it it by making the array access conditional
      to index < PT_FPSCR and using a 3rd else leg but for some reason gcc
      was unable to understand it and still spewed the warning.
      
      So I ended up with something a tad more intricated but it seems to
      build on 32-bit and on 64-bit with and without VSX.
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      e69b742a
    • Jimi Xenidis's avatar
      powerpc: Fix xmon for systems without MSR[RI] · 66857b3a
      Jimi Xenidis authored
      Based on patch by David Gibson <dwg@au1.ibm.com>
      
      xmon has a longstanding bug on systems which are SMP-capable but lack
      the MSR[RI] bit.  In these cases, xmon invoked by IPI on secondary
      CPUs will not properly keep quiet, but will print stuff, thereby
      garbling the primary xmon's output.  This patch fixes it, by ignoring
      the RI bit if the processor does not support it.
      
      There's already a version of this for 4xx upstream, which we'll need
      to extend to other RI-lacking CPUs at some point.  For now this adds
      Book3e processors to the mix.
      Signed-off-by: default avatarJimi Xenidis <jimix@pobox.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      66857b3a
  5. 26 Sep, 2011 1 commit
  6. 23 Sep, 2011 2 commits
  7. 22 Sep, 2011 7 commits
  8. 20 Sep, 2011 11 commits