- 26 Sep, 2017 40 commits
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Harry Wentland authored
Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jordan Lazare authored
When moving to a common dce/ infrastructure for all asics, some register fields do not exist in DCE8, and cause ASSERTS and debug spam. Instead, check to see whether a register field mask is valid before attempting to program the register field Signed-off-by:
Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
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Harry Wentland authored
Also make the code somewhat more readable. Signed-off-by:
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Julia Lawall authored
Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Signed-off-by:
Julia Lawall <julia.lawall@lip6.fr> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Reviewed-by:
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Julia Lawall authored
Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Signed-off-by:
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Julia Lawall authored
Remove unneeded semicolons. Generated by: scripts/coccinelle/misc/semicolon.cocci Signed-off-by:
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Jordan Lazare authored
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Zeyu Fan authored
Signed-off-by:
Zeyu Fan <Zeyu.Fan@amd.com> Acked-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Tony Cheng authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Zeyu Fan authored
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Sylvia Tsai authored
- Set ignore_msa_timing_param to 1 only for modes that can support freesync Signed-off-by:
Sylvia Tsai <sylvia.tsai@amd.com> Reviewed-by:
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Vitaly Prosyak authored
Moved custom floating point calculation to the shared place between dce's. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Reza Amini authored
Signed-off-by:
Reza Amini <reza.amini@amd.com> Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Hersen Wu authored
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Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Eagle Yeh <eagle.yeh@amd.com> Acked-by:
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Dmytro Laktyushkin authored
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Krzysztof Nowicki authored
Remove a false assumption that a cached EDID will be present whenever the connector is in a connected state as this will only be true for logical MST ports. For physical ports the EDID will never be cached, which will cause them to always appear as disconnected. This reverts commit 4ff8a88888de271bfb7750b2a5c68163848e2bf1 Signed-off-by: -
Harry Wentland authored
They might call commit with ACTION_NOTHING without a mode. We shouldn't crash but simply skip updating stream scaling settings since scaling obviously didn't change without a provided mode. Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Acked-by:
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Yongqiang Sun authored
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Vitaly Prosyak authored
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Charlene Liu authored
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Charlene Liu authored
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Hersen Wu authored
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Rex Zhu authored
Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Acked-by:
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Harry Wentland authored
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Charlene Liu authored
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Leon Elazar authored
Signed-off-by:
Leon Elazar <leon.elazar@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Anthony Koo authored
Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Reviewed-by:
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Anthony Koo authored
Fix problem with loading IRAM Signed-off-by:
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Dmytro Laktyushkin authored
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Anthony Koo authored
Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Anthony Koo authored
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Yongqiang Sun authored
Power off plane clear all the reg values includes cursor. When OS call set cursor position, cursor address reg is cleared, results in system hard hang. Signed-off-by:
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Leon Elazar authored
Fixes: 1. Removing pending flag since we are executing teh entire flow without context switches 2. Adding stream enablment - connection between DIG BE to DIG FE during test link training Signed-off-by:
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Yongqiang Sun authored
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Anthony Koo authored
1. Fix init of integer 2. Fix mixed declarations Signed-off-by:
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Andrey Grodzovsky authored
This parameter name is misleading. It's previous meaning confuses with ASYNC (immidiate flip) which is totatlly different thing then nonblocking commit. Signed-off-by:
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Harry Wentland authored
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